多核处理器内部核间通信研究

发布时间：2019-01-27 22:04

【摘要】：随着计算机的广泛应用，人们对于处理器的性能要求越来越高。传统的单核处理器仅仅依靠提高处理器的时钟频率的做法已经无法满足需求了，单芯片多核处理器（CMP）技术也就应运而生。它相比于单核单芯片处理器有控制逻辑简单、设计和验证周期短、并行处理、积木式升级、低功耗、低通信延迟等优点。多核处理器目前已经取代了单核处理器成为市场上的处理器的主流产品。多核处理器内的多个核并不是简单地相连。多核处理器内部的互联架构的研究近年来已在国内外广泛开展。本文详细分析了多核处理器发展现状及趋势，目前多核处理器内部现有的通信架构的优缺点以及它们各自的适用场合。本文针对小核模式的多核处理器提出了一种CMC总线架构。CMC总线架构的设计目标是实现总线只需一根握手信号线，简单的硬件逻辑，软件上提供必要的控制接口。本文设计出一种多核处理器的架构，该架构既适用于同构多核处理器又适用于异构多核处理器。运用该架构的多核处理器每个核处理的任务可以在很小、很专一。多核处理器内部多个核的互联总线包括有外总线、长总线、短总线。长、短总线在多核处理器内分别有各自不同的功能，长、短总线都采用CMC总线架构。整个CMC总线架构采用Verilog硬件描述语言编写实现，把多核处理器内部的各个核有机的结合在一起。利用Modelsim SE软件仿真验证多核处理器内部核间长、短总线的读写，，并在Quartus II编程环境上进行了综合和布局布线，把固件下载到了Altera的型号为Stratix II的FPGA中，然后把验证的结果和设计的要求进行了比较，判断其功能是否达到了预期的设计目标，证明该核间通信架构的可行性。该内部核间通信结构的多核处理器的研究为后续的相关产品开发和设计奠定了坚实的基础。
[Abstract]:With the wide application of computers, the performance of processors is becoming more and more demanding. The traditional single-core processor can not meet the demand only by increasing the clock frequency of the processor, and the single-chip multi-core processor (CMP) technology emerges as the times require. Compared with single-core single-chip processor, it has the advantages of simple control logic, short design and verification cycle, parallel processing, building block upgrade, low power consumption, low communication delay and so on. Multi-core processors have now replaced single-core processors as the mainstream of processors on the market. Multiple cores within a multicore processor are not simply connected. In recent years, the research of interconnect architecture in multi-core processors has been widely carried out at home and abroad. In this paper, the development status and trend of multi-core processors are analyzed in detail. The advantages and disadvantages of the existing communication architectures within multi-core processors and their respective applications are analyzed in detail. This paper presents a CMC bus architecture for multi-core processors with small core mode. The design goal of CMC bus architecture is to realize the bus with only one handshake signal line, simple hardware logic and necessary control interface in software. This paper presents an architecture of multicore processors, which is suitable for both isomorphic multicore processors and heterogeneous multicore processors. Multi-core processors using this architecture can handle tasks at very small and dedicated levels per core. The interconnection bus of multiple cores in a multi-core processor includes external bus, long bus and short bus. Long bus and short bus have different functions in multi-core processor. Long bus and short bus adopt CMC bus architecture. The whole CMC bus architecture is implemented by Verilog hardware description language, which combines the core of the multi-core processor. The Modelsim SE software is used to simulate and verify the read and write of the intercore and short bus in the multi-core processor, and the synthesis and layout wiring are carried out in the Quartus II programming environment, and the firmware is downloaded to the FPGA with the Altera model as Stratix II. Then the results of verification are compared with the requirements of the design, and the function of the architecture is judged whether it reaches the expected design goal, and the feasibility of the communication architecture between cores is proved. The research of multi-core processor with intercore communication architecture lays a solid foundation for related product development and design.
【学位授予单位】：沈阳理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

【参考文献】