高速数据存储器研制

发布时间：2019-01-30 14:58

【摘要】：飞行试验在飞行器的设计制造过程中是非常重要的一个环节。在飞行试验中,各种状态参数信号需要实时记录,通过分析数据来对飞行器的性能和技术指标进行评估和改进。并且飞行过程中试验环境复杂恶劣,这对记录数据的高速数据记录仪的设计提出了很高的要求。本文通过细致分析高速数据记录仪的需求,对国内外现状进行调研,给出了高速数据记录仪的设计方案,并对其中关键的硬件模块、软件结构和关键要点进行了进一步的说明。设计采用TI公司的一对串化解串芯片来实现LVDS(Low Voltage Differential Signal)信号的收发,在链路中间添加电缆均衡器,采取设计手段隔离信号地和参考地,使用两路独立SMA(SMall A-type)接口实现阻抗匹配,使得LVDS传输距离提高至10m以上。数据串行传输速率最高达到300Mbps。设计中采用2片FPGA控制2套硬件存储电路,增加信息记录和索引模块,设计前端高速缓存电路,实现高速数据读取。并对如何实现FPGA间数据通讯协同,进行了说明。设计采用Micron公司的单片32GB的SLC(Single Level Cell)型NANDFlash作为存储介质,8片并联组成阵列实现256GB存储。2片一组共四组,实时存储速率达到50MB/s,满足最高数据传输速率和数据容量的需求。高速数据记录仪的设计符合技术指标,并且通过了环境试验验证,在暗室测试、水平挂飞、高速俯冲以及飞行试验中,各项性能指标正常,数据记录可靠,满足使用流程要求。
[Abstract]:Flight test is a very important part in the design and manufacture of aircraft. In flight test, the signals of various state parameters need to be recorded in real time, and the performance and technical indexes of the aircraft are evaluated and improved by analyzing the data. And the test environment is complex and bad during flight, which requires the design of high speed data recorder to record data. By analyzing the demand of high speed data recorder and investigating the present situation at home and abroad, the design scheme of high speed data recorder is given in this paper, and the key hardware module, software structure and key points are further explained. In this paper, a pair of serial chips of TI Company are used to realize the transceiver of LVDS (Low Voltage Differential Signal) signal, the cable equalizer is added in the middle of the link, and the design method is adopted to isolate the signal ground and reference ground. Two independent SMA (SMall A-type) interfaces are used to realize impedance matching, which increases the transmission distance of LVDS to more than 10 m. The data serial transmission rate is up to 300 Mbps. In the design, two sets of hardware storage circuits are controlled by two pieces of FPGA, the information recording and indexing modules are added, the front-end cache circuit is designed, and the high-speed data reading is realized. And how to realize the data communication cooperation between FPGA is explained. In this paper, Micron's 32GB SLC (Single Level Cell) NANDFlash is used as storage medium, and 8 parallel arrays are used to realize 256GB storage. Two pieces are divided into four groups, and the real time storage rate is 50 MB / s. To meet the maximum data transmission rate and data capacity requirements. The design of the high-speed data recorder accords with the technical specifications, and has passed the environmental test verification. In the dark room test, the horizontal hanging flight, the high speed dive and the flight test, each performance index is normal, the data record is reliable, meets the use flow request.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2018
【分类号】：V217;TP333

【参考文献】