DDR3存储器接口电路的设计与实现

发布时间：2019-02-18 18:40

【摘要】：DDR存储器作为处理器的片外主存储器,是一种高性能、低成本的存储解决方案。DDR存储器被大量应用于PC,服务器和如今的SOC设计中。它被用来存放数据和程序,因此俗称“内存”。随着处理器技术的不断进步,存储器技术也随之不断发展。目前,业界主流已从DDR2向DDR3过渡,这是因为DDR3比DDR2不但具有更低的功耗,也具有更高的速度和容量。但是在使用DDR3内存时,设计者面临的一个主要的挑战是对高速I/O的需求。这是因为当接口速度高于1Gbps时,I/O性能变得非常关键,或将成为整个系统性能的瓶颈。因此设计高速的DDR3I/O电路已变成非常迫切的应用需求。当设计者设计DDR3 I/O时将会发现,随着接口速度的提高,数字信号将表现出越来越多的非理想性,而信号完整性也将成为设计者最主要关注之一。 DDR3 I/O是一种数模混合高速专用I/O,在设计时,接口设计者面临的主要挑战包括,他不但需要先进的深亚微米工艺提供的高速MOS开关,也需要选择合适的电路架构以实现高性能,还需要在电路设计之初就充分考虑反射和噪声等信号完整性问题,并建立合适的寄生参数模型进行仿真和优化,同时还要保证紧凑的版图设计和可靠的ESD性能。本文基于实际工程需要,设计并实现了一种DDR3 I/O,它基于中芯国际65mm低漏电工艺技术全定制开发,在1.5V工作电压下可达到800Mbps～1600Mbps数据率。它完全符合JEDEC DDR3规范,可作为专用接口IP模块,应用于DDR3内存控制器物理层中。
[Abstract]:As the main out-of-chip memory of processor, DDR memory is a high performance and low cost storage solution. DDR memory is widely used in PC, server and today's SOC design. It is used to hold data and programs, so it is commonly known as "memory". With the development of processor technology, memory technology is also developing. At present, the mainstream of the industry has transitioned from DDR2 to DDR3 because DDR3 not only has lower power consumption, but also has higher speed and capacity than DDR2. But a major challenge for designers when using DDR3 memory is the need for high-speed I / O. This is because when the interface speed is higher than 1Gbps, I / O performance becomes very critical, or will become the bottleneck of the whole system performance. Therefore, the design of high-speed DDR3I/O circuit has become a very urgent application demand. When designers design DDR3 I / O, they will find that with the increase of interface speed, digital signals will show more and more non-ideality, and signal integrity will become one of the most important concerns of designers. DDR3 I / O is a digital-to-analog hybrid high-speed dedicated I / O, and the main challenges that interface designers face in designing it include not only high speed MOS switches provided by advanced deep submicron processes. It is also necessary to select the appropriate circuit architecture to achieve high performance, and to fully consider the problems of signal integrity such as reflection and noise at the beginning of circuit design, and to establish appropriate parasitic parameter models for simulation and optimization. Also ensure compact layout design and reliable ESD performance. In this paper, we design and implement a kind of DDR3 I / O based on SMIC 65mm low leakage technology, which can achieve 800Mbps~1600Mbps data rate at 1.5V working voltage. It fully conforms to the JEDEC DDR3 specification and can be used as a special interface IP module in the physical layer of DDR3 memory controller.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN405;TP333

【共引文献】