DDR3控制器的设计与验证
发布时间：2019-02-20 08:52
【摘要】：伴随着摩尔定律，现今各种微处理器内部的工作频率不断上升，存储器有限的存取速度和外部接口的控制电路的低性能直接影响了系统性能的提升。DDR3SDRAM作为新一代存储器，有着工作电压低，功耗小，速度快和容量大等特点，，但是也存在一些局限性。DDR3SDRAM的各种读写操作必须要满足特定的时序参数，才能保证内存正常工作。DDR3SDRAM控制器采用简单的用户接口，内部实现各种复杂的DDR3的读写操作要求。 本文在研究了DDR3的工作原理和基本操作的基础上，设计出一款高性能控制器。为了提升DDR3的传输速率，采用了输入请求重排序和利用SDRAM中多个独立Bank进行并行操作等关键技术。输入请求重排序可以有效的提高页命中的概率。多个独立Bank并行执行可以有效的掩盖预充电的时间，不同Bank交叉执行可以大大降低内存访问延迟。DDR3控制器采用自顶向下的设计方法划分为各个模块，然后用VerilogHDL完成初始化模块、用户接口模块、控制模块、排序模块、写过程和读重新排序模块的RTL编码。分析了Altera数字PHY的基本性能的基础上，设计DDR3控制器与数字PHY的接口模块。搭建相应的仿真验证平台，采用随机化测试激励自动完成测试结果和预期结果的的比对，完成了DDR3控制器的主要功能的仿真验证。为以后DDR3内存控制器的设计提供了参考。
[Abstract]:With Moore's law, the internal frequency of various microprocessors is increasing, the limited memory access speed and the low performance of the external interface control circuit directly affect the performance of the system. DDR3SDRAM as a new generation of memory, It has the characteristics of low working voltage, low power consumption, high speed and large capacity, but it also has some limitations. All kinds of reading and writing operations of DDR3SDRAM must meet certain timing parameters. The DDR3SDRAM controller adopts simple user interface and realizes various complex DDR3 read and write operation requirements. On the basis of studying the working principle and basic operation of DDR3, a high performance controller is designed in this paper. In order to improve the transmission rate of DDR3, the key technologies such as reordering of input requests and parallel operation of multiple independent Bank in SDRAM are adopted. Input request reordering can effectively increase the probability of page hits. Multiple independent Bank parallel execution can effectively cover up the precharge time, different Bank cross execution can greatly reduce the memory access delay. The DDR3 controller is divided into modules by top-down design method. Then VerilogHDL is used to complete the RTL coding of initialization module, user interface module, control module, sort module, write process and read resort module. On the basis of analyzing the basic performance of Altera digital PHY, the interface module between DDR3 controller and digital PHY is designed. The corresponding simulation verification platform is built and the simulation verification of the main functions of the DDR3 controller is completed by automatically comparing the test results with the expected results by using the randomization test excitation. It provides a reference for the design of DDR3 memory controller in the future.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
本文编号：2427025
[Abstract]:With Moore's law, the internal frequency of various microprocessors is increasing, the limited memory access speed and the low performance of the external interface control circuit directly affect the performance of the system. DDR3SDRAM as a new generation of memory, It has the characteristics of low working voltage, low power consumption, high speed and large capacity, but it also has some limitations. All kinds of reading and writing operations of DDR3SDRAM must meet certain timing parameters. The DDR3SDRAM controller adopts simple user interface and realizes various complex DDR3 read and write operation requirements. On the basis of studying the working principle and basic operation of DDR3, a high performance controller is designed in this paper. In order to improve the transmission rate of DDR3, the key technologies such as reordering of input requests and parallel operation of multiple independent Bank in SDRAM are adopted. Input request reordering can effectively increase the probability of page hits. Multiple independent Bank parallel execution can effectively cover up the precharge time, different Bank cross execution can greatly reduce the memory access delay. The DDR3 controller is divided into modules by top-down design method. Then VerilogHDL is used to complete the RTL coding of initialization module, user interface module, control module, sort module, write process and read resort module. On the basis of analyzing the basic performance of Altera digital PHY, the interface module between DDR3 controller and digital PHY is designed. The corresponding simulation verification platform is built and the simulation verification of the main functions of the DDR3 controller is completed by automatically comparing the test results with the expected results by using the randomization test excitation. It provides a reference for the design of DDR3 memory controller in the future.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
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本文编号：2427025
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