高速低功耗SRAM的设计与实现
发布时间：2019-03-13 16:59
【摘要】：静态随机访问存储器（SRAM）作为最重要的半导体存储器，广泛地嵌入于高性能微处理器。随着集成电路制造工艺的不断提升，存储器占据芯片的功耗比例越来越大，高速低功耗的SRAM设计变得越来越重要。 本文结合全定制设计、基于标准单元设计而通过人工布局布线实现的半定制设计流程，对高速低功耗SRAM的设计、实现与验证技术进行了研究，具体包括： （1）65nm工艺下高速SRAM的设计与实现 SRAM基于带异步复位端的13管1W/1R存储单元，具有较高的读操作稳定性和较低的漏电流，但它的写入延时和版图面积大。为了弥补这些缺陷，针对双位线的写入结构，本文提出了位线共享的低功耗位线策略。读译码和数据读出通路以牺牲面积和功耗获得了更快的读出速度，这使得实现的SRAM与MemoryCompiler生成的相同容量的SRAM相比，，输出延时减小了41.62%。在实现方式上，SRAM的外围电路采用标准单元设计而通过人工布局布线实现，缩短了设计周期。本文运用脚本语言开发了具有高仿真精度的电路和版图的自动化验证流程。 （2）40nm工艺下高速低功耗SRAM的设计与实现 SRAM基于10管1W/2R存储单元，采用了两级动态译码、层次的动态预充的读出结构、LSDL电路、脉冲和门控时钟等高速低功耗设计技术。本文对动态初级译码的可靠性、动态译码电路和动态预充的读出结构存在的漏电流进行了分析与优化，保证了SRAM可以在较低的频率（20MHz）下正常工作。实现结果表明，与Memory Compiler生成的同规格SRAM相比，全定制设计的SRAM，面积减小了7.67%，延时减少了35.33%，功耗降低了39.66%。 本文设计的存储体，达到了两款DSP芯片对嵌入式SRAM的性能要求，并为进一步研究双端口8管或者带有异步复位端的高速低功耗SRAM奠定了基础。
[Abstract]:As the most important semiconductor memory, static random access memory (SRAM) is widely embedded in high performance microprocessors. With the development of IC manufacturing technology, memory occupies more and more power consumption, and high-speed and low-power SRAM design becomes more and more important. In this paper, the design, implementation and verification technology of high-speed and low-power SRAM are studied based on the semi-custom design flow, which is based on standard cell design and realized by manual layout and routing. The main contents are as follows: (1) the design and implementation of high-speed SRAM in 65nm process is based on 13-tube 1W/1R memory cell with asynchronous reset end, which has high read stability and low leakage current. However, it has a large write delay and large layout area. In order to make up for these defects, aiming at the write structure of two-bit line, this paper proposes a low-power bit-line sharing strategy for bit-line sharing. The read decoding and data readout paths achieve faster readout speed at the expense of area and power consumption, which reduces the output delay of the implemented SRAM by 41.62% compared with the SRAM of the same capacity generated by the MemoryCompiler. In the way of realization, the peripheral circuit of SRAM is designed by standard cell and realized by manual layout and routing, which shortens the design period. In this paper, the automatic verification flow of circuit and layout with high simulation precision is developed by script language. (2) the design and implementation of high-speed and low-power SRAM in 40nm process SRAM is based on 10-transistor 1W/2R memory cell, two-stage dynamic decoding, hierarchical dynamic precharge readout structure and LSDL circuit are adopted. High-speed and low-power design techniques such as pulse and gated clock. In this paper, the reliability of the dynamic primary decoding, the leakage current existing in the dynamic decoding circuit and the readout structure of the dynamic precharge are analyzed and optimized, so that the SRAM can work normally at a lower frequency (20MHz). The results show that the SRAM, area, delay and power consumption of the full-custom design are reduced by 7.67%, 35.33% and 39.66%, respectively, compared with the standard SRAM generated by Memory Compiler. The memory bank designed in this paper meets the performance requirements of two DSP chips for embedded SRAM, and lays a foundation for further research on dual-port 8-tube or high-speed and low-power SRAM with asynchronous reset.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
本文编号：2439588
[Abstract]:As the most important semiconductor memory, static random access memory (SRAM) is widely embedded in high performance microprocessors. With the development of IC manufacturing technology, memory occupies more and more power consumption, and high-speed and low-power SRAM design becomes more and more important. In this paper, the design, implementation and verification technology of high-speed and low-power SRAM are studied based on the semi-custom design flow, which is based on standard cell design and realized by manual layout and routing. The main contents are as follows: (1) the design and implementation of high-speed SRAM in 65nm process is based on 13-tube 1W/1R memory cell with asynchronous reset end, which has high read stability and low leakage current. However, it has a large write delay and large layout area. In order to make up for these defects, aiming at the write structure of two-bit line, this paper proposes a low-power bit-line sharing strategy for bit-line sharing. The read decoding and data readout paths achieve faster readout speed at the expense of area and power consumption, which reduces the output delay of the implemented SRAM by 41.62% compared with the SRAM of the same capacity generated by the MemoryCompiler. In the way of realization, the peripheral circuit of SRAM is designed by standard cell and realized by manual layout and routing, which shortens the design period. In this paper, the automatic verification flow of circuit and layout with high simulation precision is developed by script language. (2) the design and implementation of high-speed and low-power SRAM in 40nm process SRAM is based on 10-transistor 1W/2R memory cell, two-stage dynamic decoding, hierarchical dynamic precharge readout structure and LSDL circuit are adopted. High-speed and low-power design techniques such as pulse and gated clock. In this paper, the reliability of the dynamic primary decoding, the leakage current existing in the dynamic decoding circuit and the readout structure of the dynamic precharge are analyzed and optimized, so that the SRAM can work normally at a lower frequency (20MHz). The results show that the SRAM, area, delay and power consumption of the full-custom design are reduced by 7.67%, 35.33% and 39.66%, respectively, compared with the standard SRAM generated by Memory Compiler. The memory bank designed in this paper meets the performance requirements of two DSP chips for embedded SRAM, and lays a foundation for further research on dual-port 8-tube or high-speed and low-power SRAM with asynchronous reset.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333
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