字线脉冲控制解决异步双端口SRAM中的写干扰
发布时间：2019-03-26 14:09
【摘要】：为了避免双端口SRAM中由写干扰造成的数据写入困难,利用写干扰的时钟偏移相关性提出了一种新的字线脉冲控制技术,确定了写干扰下成功写入数据所需的最小写字线脉宽,并设计了时钟沿检测电路来解决写操作造成的写干扰.采用TSN28HPM工艺,抽取RC寄生参数后进行了后端仿真,结果表明所提方案可行有效.
[Abstract]:In order to avoid the data writing difficulty caused by write interference in dual-port SRAM, a new word line pulse control technique is proposed by using the clock offset correlation of write interference, and the minimum writing line pulse width required for successful write data under write interference is determined. And the clock edge detection circuit is designed to solve the write interference caused by write operation. The TSN28HPM process is used to extract the parasitic parameters of RC and the back-end simulation is carried out. The results show that the proposed scheme is feasible and effective.
【作者单位】： 上海交通大学微电子学院;
【分类号】：TP333
本文编号：2447625
[Abstract]:In order to avoid the data writing difficulty caused by write interference in dual-port SRAM, a new word line pulse control technique is proposed by using the clock offset correlation of write interference, and the minimum writing line pulse width required for successful write data under write interference is determined. And the clock edge detection circuit is designed to solve the write interference caused by write operation. The TSN28HPM process is used to extract the parasitic parameters of RC and the back-end simulation is carried out. The results show that the proposed scheme is feasible and effective.
【作者单位】： 上海交通大学微电子学院;
【分类号】：TP333
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，本文编号：2447625
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