动态可切换流水线RISC-V处理器建模与实现

发布时间：2019-03-27 07:17

【摘要】：随着微电子、信息、通信及网络技术的发展,物联网已在健康医疗、人工智能、网络管理、物流运输等领域逐步得到应用。在这些应用中,信息的采集及处理是物联网技术的基础和关键。由于物联网的信息懫集及处理节点分布广、不宜更换电源,因此,低功耗的信息采集及处理芯片是保证物联网正常工作的关键。本文在分析不同应用场景下物联网对处理器的不同要求,并研究高性能处理器的低功耗设计技术后,为平衡物联网应用中的高性能和低功耗需求,提出了一种动态可切换流水线的处理器设计方案。首先,该方案中采用RISC-V指令集,基于经典流水线架构重新细分流水,设计了适用于高性能模式的七级超流水结构其次,将其简化后实现了适用于低功耗模式的精简结构。最后,基于以上两种结构设计了动态可切换流水线的RISC-V处理器。在整体系统中两种模式共享内存、缓存及ALU执行单元,并确定了对应的软件调度策略完成程序执行过程中的数据交互及任务切换。在整个实现过程中,首先对该结构采用SystemC进行周期精确型建模,然后使用Verilog语言实现硬件电路,最后对模型进行功能仿真及相应的性能功耗分析。其中,基于本文结构中的高性能模式单核处理器已使用中芯国际180nm工艺完成流片,并对其进行了测试。本文以自建的加法、矩阵乘法及标准测试程序DMIPS、CRC、AES作为测试向量对系统进行功能仿真,并使用HP Labs的McPAT及Synopsys的DC分别从系统级和电路级进行性能功耗分析。当应用于物联网时,相比于单独的高性能处理器,本文提出的处理器结构在硬件资源仅增加5%的情况下就可以实现设计要求,同时系统功耗会降低67.23%,而且数据采集阶段所占的时间比例越长,该设计结构对系统整体功耗的降低效果越明显。
[Abstract]:With the development of microelectronics, information, communication and network technology, the Internet of things has been gradually applied in the fields of health care, artificial intelligence, network management, logistics and transportation. In these applications, the collection and processing of information is the basis and key of Internet of things technology. Because of the wide distribution of the information collection and processing nodes of the Internet of things, it is not suitable to replace the power supply. Therefore, the low-power information acquisition and processing chip is the key to ensure the normal work of the Internet of things. After analyzing the different requirements of Internet of things on processors in different application scenarios, and studying the low-power design technology of high-performance processors, this paper balances the requirements of high-performance and low-power in Internet of things applications. A design scheme of dynamic switchable pipeline processor is presented in this paper. Firstly, the scheme adopts RISC-V instruction set and re-subdivides pipelining based on classical pipelined architecture, and then designs a seven-stage super-pipelined architecture suitable for high-performance mode, and then simplifies it to implement a reduced structure suitable for low-power mode. Finally, a dynamic switchable pipelined RISC-V processor is designed based on the above two architectures. In the whole system, the two modes share memory, cache and ALU execution unit, and determine the corresponding software scheduling strategy to complete the data interaction and task switching in the process of program execution. In the whole implementation process, SystemC is used to build the precise periodic model, then Verilog language is used to realize the hardware circuit. Finally, the function simulation and performance power analysis of the model are carried out. Among them, based on the high-performance mode single-core processor in the architecture of this paper, the chip has been completed by using the SMIC 180nm process, and the chip has been tested. In this paper, we use self-built addition, matrix multiplication and standard test program DMIPS,CRC,AES as test vectors to simulate the function of the system, and use McPAT of HP Labs and DC of Synopsys to analyze performance power consumption from system level and circuit level, respectively. When applied to the Internet of things, compared with the single high-performance processor, the proposed processor architecture can achieve the design requirements with only 5% increase in hardware resources, and at the same time, the system power consumption will be reduced by 67.23%. Moreover, the longer the time of the data acquisition phase is, the more obvious the design structure can reduce the overall power consumption of the system.
【学位授予单位】：西安理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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