数据中心中DVFS对程序性能影响模型的设计
发布时间：2019-04-23 13:38
【摘要】：数据中心以可接受的成本,承载着超大规模的互联网应用.数据中心的能源消耗直接影响着数据中心的一次性建造成本和长期维护成本,是数据中心总体持有成本的重要组成部分.现代的数据中心普遍采用动态电压频率调节(dynamic voltage frequency scaling,简称DVFS)来提升单节点的能耗表现.但是,DVFS这一类机制同时影响到应用的能源消耗和性能,而这一问题尚未被深入探索.专注于DVFS机制对应用程序性能的影响,提出了一个分析模型用来量化地刻画应用程序的性能与处理器频率之间的关系,可以预测程序在任意频率下的性能.具体来说,依据执行时访问内存子系统资源的不同,把程序的指令分为两部分——片上指令和片外指令,并分别独立建模.片上指令是指仅需访问片上资源就可以完成执行的指令,其执行时间与处理器频率呈线性关系;片外指令是指需要访问主存的指令,其执行时间与处理器频率无关.通过上述划分和对每一部分执行时间的分别建模,可以获得应用程序的执行时间与处理器频率之间的量化模型.使用两个不同的平台和SPEC 2006中的所有标准程序验证该模型,平均误差不超过1.34%.
[Abstract]:Data centers carry ultra-large-scale Internet applications at an acceptable cost. The energy consumption of the data center directly affects the one-time construction cost and the long-term maintenance cost of the data center, and it is an important part of the total holding cost of the data center. Dynamic voltage frequency regulation (dynamic voltage frequency scaling,) is widely used in modern data centers to improve the performance of single node energy consumption. However, such mechanisms as DVFS affect the energy consumption and performance of applications at the same time, and this problem has not been deeply explored. Focusing on the effect of DVFS mechanism on application performance, an analytical model is proposed to quantitatively describe the relationship between application performance and processor frequency, which can predict the performance of applications at any frequency. Specifically, according to the different resources of accessing memory subsystem during execution, the instruction of the program is divided into two parts-on-chip instruction and out-of-chip instruction, and is modeled independently. On-chip instruction refers to instructions that can be executed only by accessing on-chip resources, and its execution time is linearly related to processor frequency, while out-of-chip instructions refer to instructions that need to access main memory, and their execution time is independent of processor frequency. The quantization model between the execution time of the application and the frequency of the processor can be obtained by the above partition and the modeling of each part of the execution time. The model was validated using two different platforms and all the standard programs in SPEC 2006 with an average error of not more than 1.34%.
【作者单位】： 计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院大学计算机控制与工程学院;
【基金】：国家重点基础研究发展计划(973)(2016YFB1000402) 国家高技术研究发展计划(863)(2015AA015306) 国家自然科学基金(61672492,61432016,61402445,61521092)~~
【分类号】：TP308
[Abstract]:Data centers carry ultra-large-scale Internet applications at an acceptable cost. The energy consumption of the data center directly affects the one-time construction cost and the long-term maintenance cost of the data center, and it is an important part of the total holding cost of the data center. Dynamic voltage frequency regulation (dynamic voltage frequency scaling,) is widely used in modern data centers to improve the performance of single node energy consumption. However, such mechanisms as DVFS affect the energy consumption and performance of applications at the same time, and this problem has not been deeply explored. Focusing on the effect of DVFS mechanism on application performance, an analytical model is proposed to quantitatively describe the relationship between application performance and processor frequency, which can predict the performance of applications at any frequency. Specifically, according to the different resources of accessing memory subsystem during execution, the instruction of the program is divided into two parts-on-chip instruction and out-of-chip instruction, and is modeled independently. On-chip instruction refers to instructions that can be executed only by accessing on-chip resources, and its execution time is linearly related to processor frequency, while out-of-chip instructions refer to instructions that need to access main memory, and their execution time is independent of processor frequency. The quantization model between the execution time of the application and the frequency of the processor can be obtained by the above partition and the modeling of each part of the execution time. The model was validated using two different platforms and all the standard programs in SPEC 2006 with an average error of not more than 1.34%.
【作者单位】： 计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院大学计算机控制与工程学院;
【基金】：国家重点基础研究发展计划(973)(2016YFB1000402) 国家高技术研究发展计划(863)(2015AA015306) 国家自然科学基金(61672492,61432016,61402445,61521092)~~
【分类号】：TP308
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