低成本的USB2.0主机控制器与驱动程序设计
发布时间：2019-04-27 00:56
【摘要】：由于USB具有传输速度快,支持热插拔,使用灵活等优良特性,已经成为一种应用非常广泛的串行接口标准,差不多有电子设备的地方就有USB。正因为如此,有不少企业或研究单位,投入大量的人力与物力,参入到USB相关的硬件与软件的研究与开发,期望在自己的产品中加入USB的功能,以提高产品的竞争力,除了要达到所需的USB性能,还不能增加太多的成本。于是提出了开发低成本USB2.0主机控制器的课题。 本论文首先讨论了USB2.0与UTMI等相关的协议,然后分析了市场上主要几类主机控制器(UHCI、OHCI、EHCI、xHCI和其它厂商或个人自行定义的)及相关协议标准或硬件与软件设计方案。并以此为基础,提出新的低成本的USB2.0主机控制器的硬件与软件设计方案。 硬件设计方案部分包含USB2.0主机控制器的架构,软硬件寄存器接口定义及AHB从机接口模块(usb20_sl_if)、DMA控制模块(usb20_dma_ctl)、缓冲管理模块(buffer_manage)、协议层控制模块(usb20_host_pl)、主机寄存器模块(usb20_host_reg)、集线器控制模块(usb20_port_ctl)等各功能子模块功能及状态转换描述,并用Verilog HDL实现。 软件设计方案部分,只设计了与硬件相关的主机控制器驱动程序部分,与硬件无关的USB协议栈与客户端软件可以直接复用Linux内核中的相关程序。主机控制器驱动程序包含了USBD接口模块、根集线器模块、数据传输模块、中断管理模块等子模块功能及函数描述,并用C语言实现。 此外还定性分析了此方案确实会比UHCI、 OHCI、 EHCI、xHCI等主机控制器的硬件成本低,也定性分析了此方案在存储类设备方面的性能不会逊色于UHCI、 OHCI、 EHCI、xHCI等主机控制器。为了保证此方案的主机控制器的高性能,实现了两点创新：一是用两个单端口SRAM来实现异步时钟域的乒乓缓冲；二是利用DMA读写数据传输与USB传输的流水线并行操作,从而提高USB总线的带宽利用率或降低对系统总线的带宽的要求。 最后采用基于BFM的自动化的验证方法,对USB2.0主机控制器的低速、全速、高速的数据传输,总线复位及DMA等相关模式及操作做了完整的验证,都符合USB2.0及UTMI协议标准。同时还用Synopsys的Design Compile综合工具,对USB2.0主机控制器的RTL综合出来的电路只有7.5千门(不包含SRAM面积)。结果表明,此方案是可行的,能同时满足低成本高性能的需求,达到了预期的目标。
[Abstract]:USB has become a very widely used serial interface standard because of its high transmission speed, hot-swappable support, flexible use, and so on. There is USB. almost where there are electronic devices. Because of this, many enterprises or research institutions have invested a great deal of manpower and material resources in the research and development of hardware and software related to USB, hoping to add the function of USB in their own products, in order to improve the competitiveness of their products. In addition to achieving the required USB performance, there is not much to add to the cost. Therefore, the subject of developing low-cost USB2.0 host controller is put forward. This paper first discusses the protocols related to USB2.0 and UTMI, and then analyzes the main types of host controllers (defined by UHCI,OHCI,EHCI,xHCI and other manufacturers or individuals) in the market as well as related protocol standards or hardware and software design schemes. Based on this, a new hardware and software design scheme of low-cost USB2.0 host controller is proposed. The hardware design includes USB2.0 host controller architecture, hardware and software register interface definition and AHB slave interface module (usb20_sl_if), DMA control module (usb20_dma_ctl), buffer management module (buffer_manage). Protocol layer control module (usb20_host_pl), host register module (usb20_host_reg), hub control module (usb20_port_ctl) and other functional sub-modules function and state transition description, and implemented with Verilog HDL. In the software design part, only the hardware-related host controller driver is designed. The hardware-independent USB protocol stack and the client software can directly reuse the related programs in the Linux kernel. Host controller driver includes USBD interface module, root hub module, data transmission module, interrupt management module and other sub-module functions and function description, and implemented in C language. In addition, the hardware cost of this scheme is lower than that of UHCI, OHCI, EHCI,xHCI and other host controllers, and the performance of this scheme is not inferior to that of UHCI, OHCI, EHCI,xHCI and other host controllers. In order to ensure the high performance of the host controller, two innovations are realized: one is to use two single-port SRAM to realize the ping-pong buffer of asynchronous clock domain; The other is to use the pipelined parallel operation of DMA read-write data transmission and USB transmission, so as to improve the bandwidth utilization of USB bus or reduce the requirement of system bus bandwidth. Finally, the automatic verification method based on BFM is used to verify the low-speed, full-speed, high-speed data transmission, bus reset, DMA and other related modes and operations of the USB2.0 host controller. All of them conform to the standards of USB2.0 and UTMI protocol. At the same time, using the Design Compile synthesis tool of Synopsys, only 7.5 thousand gates (excluding the SRAM area) are integrated from the RTL of the USB2.0 host controller. The results show that this scheme is feasible and can meet the requirements of low-cost and high-performance at the same time.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.3
本文编号：2466544
[Abstract]:USB has become a very widely used serial interface standard because of its high transmission speed, hot-swappable support, flexible use, and so on. There is USB. almost where there are electronic devices. Because of this, many enterprises or research institutions have invested a great deal of manpower and material resources in the research and development of hardware and software related to USB, hoping to add the function of USB in their own products, in order to improve the competitiveness of their products. In addition to achieving the required USB performance, there is not much to add to the cost. Therefore, the subject of developing low-cost USB2.0 host controller is put forward. This paper first discusses the protocols related to USB2.0 and UTMI, and then analyzes the main types of host controllers (defined by UHCI,OHCI,EHCI,xHCI and other manufacturers or individuals) in the market as well as related protocol standards or hardware and software design schemes. Based on this, a new hardware and software design scheme of low-cost USB2.0 host controller is proposed. The hardware design includes USB2.0 host controller architecture, hardware and software register interface definition and AHB slave interface module (usb20_sl_if), DMA control module (usb20_dma_ctl), buffer management module (buffer_manage). Protocol layer control module (usb20_host_pl), host register module (usb20_host_reg), hub control module (usb20_port_ctl) and other functional sub-modules function and state transition description, and implemented with Verilog HDL. In the software design part, only the hardware-related host controller driver is designed. The hardware-independent USB protocol stack and the client software can directly reuse the related programs in the Linux kernel. Host controller driver includes USBD interface module, root hub module, data transmission module, interrupt management module and other sub-module functions and function description, and implemented in C language. In addition, the hardware cost of this scheme is lower than that of UHCI, OHCI, EHCI,xHCI and other host controllers, and the performance of this scheme is not inferior to that of UHCI, OHCI, EHCI,xHCI and other host controllers. In order to ensure the high performance of the host controller, two innovations are realized: one is to use two single-port SRAM to realize the ping-pong buffer of asynchronous clock domain; The other is to use the pipelined parallel operation of DMA read-write data transmission and USB transmission, so as to improve the bandwidth utilization of USB bus or reduce the requirement of system bus bandwidth. Finally, the automatic verification method based on BFM is used to verify the low-speed, full-speed, high-speed data transmission, bus reset, DMA and other related modes and operations of the USB2.0 host controller. All of them conform to the standards of USB2.0 and UTMI protocol. At the same time, using the Design Compile synthesis tool of Synopsys, only 7.5 thousand gates (excluding the SRAM area) are integrated from the RTL of the USB2.0 host controller. The results show that this scheme is feasible and can meet the requirements of low-cost and high-performance at the same time.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.3
【参考文献】
相关期刊论文 前1条
1 马伟;嵌入式USB主机系统的研究与设计[J];计算机测量与控制;2003年05期
相关硕士学位论文 前8条
1 尹涛;面向SoC的USB控制器IP核设计[D];青岛科技大学;2005年
2 武甲东;基于龙芯SoC的USB主机控制器的设计研究[D];山东科技大学;2005年
3 姚建平;USB主机控制芯片的逻辑设计与验证[D];中国科学院研究生院（计算技术研究所）;2005年
4 廖文兵;USB2.0 OTG IP核全速主机控制器研究与设计[D];电子科技大学;2008年
5 程峗;用于IP电话的32位微控制器中USB2.0主机控制器的设计[D];华中科技大学;2008年
6 金腾;USB2.0主机控制器ASIC设计[D];北京交通大学;2009年
7 胡立琴;嵌入式USB2.0主机控制器IP核设计与实现[D];湖南大学;2009年
8 余勇志;嵌入式USB主机控制器的研究与设计[D];重庆大学;2009年
，本文编号：2466544
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2466544.html
