基于异步NoC机制的Booth乘法器设计

发布时间：2019-04-28 19:02

【摘要】：随着信息化社会的深入发展,数字集成电路技术运用得越来越广泛.乘法器是数字电路系统最重要的算术运算单元之一,影响了整个电路系统的工作效率.实际设计通常采用Booth结构作为数字乘法器实现框架,决定此类乘法器运算效率的最为关键的两个方面是:部分积产生和部分积合并.提出了一种从结构上采用独立路由寻址的机制来实现部分积的产生,设计方法上采用异步微流水线,控制机制上采取数据通路的方法,来设计基于异步NoC(Network On Chip)机制的Booth乘法器设计.最后,通过FPGA开发板进行了仿真和实现,并与传统的Booth乘法器性能做了对比分析.
[Abstract]:With the in-depth development of information society, digital integrated circuit technology is more and more widely used. Multiplier is one of the most important arithmetic operation units in digital circuit system, which affects the working efficiency of the whole circuit system. In practical design, Booth structure is usually used as the implementation framework of digital multipliers. The most important aspects to determine the computational efficiency of such multipliers are: partial product generation and partial integration. In this paper, an independent routing addressing mechanism is proposed to realize the generation of partial product. The asynchronous micropipeline is used in the design method, and the data path is adopted in the control mechanism. To design the Booth multiplier design based on asynchronous NoC (Network On Chip) mechanism. Finally, the simulation and implementation of the FPGA development board are carried out, and the performance of the traditional Booth multiplier is compared and analyzed.
【作者单位】：广西民族大学广西混杂计算与集成电路设计分析重点实验室;兰州大学信息科学与工程学院;北京计算机技术及应用研究所;
【基金】：国家自然科学基金(11371003,11461006,61402121) 广西民族大学校级一般项目(2016YB029);广西民族大学研究生教育创新计划项目;广西民族大学相思湖青年学者创新团队资助
【分类号】：TP332.22

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