面向高性能计算的众核处理器轻量级错误恢复技术研究

发布时间：2019-05-14 11:06

【摘要】：随着半导体技术进步,单个芯片上集成大量核心的众核处理器已经广泛应用于高性能计算领域.相比多核处理器,众核处理器能提供更好的计算密度和能效比,但同时也面临越来越严重的可靠性挑战.需要设计高效的处理器容错机制,有效保证课题运行效率的同时不带来较大的芯片功耗和面积开销.在一款自主众核处理器DFMC(deeply fused and heterogeneous many-core)原型基础上,根据核心上运行的应用程序是否具有关联性特征,提出并实现了面向众核处理器的独立和协同2种轻量级错误恢复技术.其中,协同恢复技术由集中部件进行管理,通过协同恢复总线互连,出错时将与错误相关联的多个核心快速回卷到正确状态.2种错误恢复技术中,保留和恢复过程均通过定制的指令实现,恢复所需要的信息保留在运算核心内部,以保证对课题性能的影响最小化.实验表明,通过上述技术只增加了1.257%的芯片面积,可解决自主众核处理器约80%的瞬时错误,且对课题性能、芯片时序和功耗影响很小,可有效地提高众核处理器的容错能力.
[Abstract]:With the progress of semiconductor technology, a large number of core processors integrated on a single chip have been widely used in the field of high performance computing. Compared with multi-core processors, multi-core processors can provide better computing density and energy efficiency ratio, but also face more and more serious reliability challenges. It is necessary to design an efficient processor fault-tolerant mechanism to effectively ensure the running efficiency of the project without bringing large chip power consumption and area overhead. Based on a prototype of an autonomous multicore processor DFMC (deeply fused and heterogeneous many-core, depending on whether the application running on the core has the characteristics of relevance, Two lightweight error recovery technologies, independent and cooperative, are proposed and implemented for multi-core processors. Among them, the cooperative recovery technology is managed by the centralized components, and through the collaborative recovery bus interconnection, multiple cores associated with the error are quickly rolled back to the correct state in the event of an error. Both the retention and recovery processes are realized by custom instructions, and the information needed for recovery is retained in the core of the operation to ensure that the impact on the performance of the project is minimized. The experimental results show that only 1.257% of the chip area is increased by the above technology, which can solve the instantaneous error of about 80% of the independent multi-core processor, and has little effect on the performance, chip timing and power consumption of the project. It can effectively improve the fault-tolerant ability of multi-core processors.
【作者单位】：数学工程与先进计算国家重点实验室;
【基金】：国家“八六三”高技术研究发展计划基金项目(2014AA01A301) “核高基”国家科技重大专项基金项目(2013ZX0102-8001-001-001)
【分类号】：TP332

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