天文图像差异算法专用硬件设计与SOC实现
发布时间：2019-05-15 20:42
【摘要】：随着处理器技术的飞速发展,微处理器在一定程度上有了很大的应用范围,而可配置处理器可以对具体应用进行适当配置,从而可以得到不同运算模块的硬件电路。通过对其进行编程管理,达到最终功能的实现。用可配置处理器完成数据密集型的运算任务时,比通用微处理器具有更强的计算能力,比ASIC(Application Specific Integrated Circuit)架构具有更大的灵活性,可加快研发周期,同时在功耗方面低于通用数字信号处理器。本论文设计了一个面向天文图像差异算法的可配置处理器—传输触发架构(TTA,Transport-Triggered Architecture)的T*Core模型。选择应用之后,根据配置相关的参数就可生成一款针对特定领域的T*Core处理器的硬件电路。 本论文对天文图像差异算法进行详细的归纳与分析,对降晰函数,核函数以及相关的求解方法,不同天空背景环境下的情况进行分析处理。这些分析,为T*Core处理器的功能单元设计提供算法的依据,T*Core的结构包含整体架构设计、内部核心单元、指令格式、流水线、网络通路、存储器和最终的系统编址等。其中基于算法的功能单元是影响整个处理器的关键部件,对数据处理的实时性起关键作用,有效合理的对其优化,更可以提高系统整体的速度。 在硬件验证中,本论文利用XILINX FPGA的XUPV5-LX110T系列MACROBLAZE作为主处理器,T*Core为协处理器,搭建一个嵌入式SOC(System on Chip)开发系统。通过SOC实现后,系统频率最终跑到100M以上。T*Core处理器的硬件架构设计已经通过了前期的仿真、验证及最后的板级系统调试。为了进一步提高速度,本文采用多核异构T*Core处理器的并行处理方案,这可以充分发挥T*Core处理器的数据密集型运算的特点。通过最后的SOC实现,T*Core处理器和普通的PC机软件实现相比,在功能正确的基础上,计算速度得到有效提高。功耗得到大大降低,双核功耗仅为软件实现时的2.3%。通过这种架构实现,再次证明了T*Core处理器可以达到实时性和低功耗的要求。
[Abstract]:With the rapid development of processor technology, microprocessors have a wide range of applications to a certain extent, and the configurable processor can properly configure the specific applications, so that the hardware circuits of different operation modules can be obtained. Through the programming management, to achieve the final function of the realization. When using a configurable processor to complete data-intensive computing tasks, it has stronger computing power than a general-purpose microprocessor, has greater flexibility than the ASIC (Application Specific Integrated Circuit) architecture, and can speed up the research and development cycle. At the same time, the power consumption is lower than that of the general digital signal processor. In this paper, a T*Core model of transmission trigger architecture (TTA,Transport-Triggered Architecture) for astronomical image difference algorithm is designed. After selecting the application, a domain-specific T*Core processor hardware circuit can be generated according to the configuration-related parameters. In this paper, the astronomical image difference algorithm is summarized and analyzed in detail, and the blurring function, kernel function and related solving methods are analyzed and processed in different sky background environment. These analyses provide the basis for the functional unit design of T*Core processor. The structure of T*Core includes the overall architecture design, internal core unit, instruction format, pipeline, network path, memory and final system addressing. Among them, the functional unit based on the algorithm is the key component that affects the whole processor, which plays a key role in the real-time performance of data processing. The effective and reasonable optimization of the function unit can improve the overall speed of the system. In the hardware verification, this paper uses XUPV5-LX110T series MACROBLAZE of XILINX FPGA as the main processor and T*Core as the coprocessor to build an embedded SOC (System on Chip) development system. After the implementation of SOC, the frequency of the system finally runs above 100m. The hardware architecture design of T * Core processor has passed the previous simulation, verification and final board level system debugging. In order to further improve the speed, this paper adopts the parallel processing scheme of multi-core heterogeneous T*Core processor, which can give full play to the characteristics of data-intensive operation of T*Core processor. Through the final SOC implementation, compared with the ordinary PC software implementation, the calculation speed of T*Core processor is effectively improved on the basis of correct function. The power consumption is greatly reduced, and the dual-core power consumption is only 2.3% of that of the software. Through this architecture, it is proved that T*Core processor can meet the requirements of real-time and low power consumption.
【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TP368.1
本文编号：2477742
[Abstract]:With the rapid development of processor technology, microprocessors have a wide range of applications to a certain extent, and the configurable processor can properly configure the specific applications, so that the hardware circuits of different operation modules can be obtained. Through the programming management, to achieve the final function of the realization. When using a configurable processor to complete data-intensive computing tasks, it has stronger computing power than a general-purpose microprocessor, has greater flexibility than the ASIC (Application Specific Integrated Circuit) architecture, and can speed up the research and development cycle. At the same time, the power consumption is lower than that of the general digital signal processor. In this paper, a T*Core model of transmission trigger architecture (TTA,Transport-Triggered Architecture) for astronomical image difference algorithm is designed. After selecting the application, a domain-specific T*Core processor hardware circuit can be generated according to the configuration-related parameters. In this paper, the astronomical image difference algorithm is summarized and analyzed in detail, and the blurring function, kernel function and related solving methods are analyzed and processed in different sky background environment. These analyses provide the basis for the functional unit design of T*Core processor. The structure of T*Core includes the overall architecture design, internal core unit, instruction format, pipeline, network path, memory and final system addressing. Among them, the functional unit based on the algorithm is the key component that affects the whole processor, which plays a key role in the real-time performance of data processing. The effective and reasonable optimization of the function unit can improve the overall speed of the system. In the hardware verification, this paper uses XUPV5-LX110T series MACROBLAZE of XILINX FPGA as the main processor and T*Core as the coprocessor to build an embedded SOC (System on Chip) development system. After the implementation of SOC, the frequency of the system finally runs above 100m. The hardware architecture design of T * Core processor has passed the previous simulation, verification and final board level system debugging. In order to further improve the speed, this paper adopts the parallel processing scheme of multi-core heterogeneous T*Core processor, which can give full play to the characteristics of data-intensive operation of T*Core processor. Through the final SOC implementation, compared with the ordinary PC software implementation, the calculation speed of T*Core processor is effectively improved on the basis of correct function. The power consumption is greatly reduced, and the dual-core power consumption is only 2.3% of that of the software. Through this architecture, it is proved that T*Core processor can meet the requirements of real-time and low power consumption.
【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TP368.1
【参考文献】
相关期刊论文 前2条
1 赵学秘;王志英;岳虹;陆洪毅;戴葵;;TTA-EC:一种基于传输触发体系结构的ECC整体算法处理器[J];计算机学报;2007年02期
2 罗公亮;核函数方法(上)[J];冶金自动化;2002年03期
相关博士学位论文 前1条
1 杨君;专用指令集处理器（ASIP）体系结构设计研究[D];中国科学技术大学;2006年
，本文编号：2477742
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