基于EJTAG的OCD调试方案的研究与实现
发布时间：2019-05-22 04:16
【摘要】：随着我国集成电路技术的不断发展，越来越多由我国自主研发的国产SoC芯片出现在市场当中。本课题的研究对象SoC CPU Core就是由我国研发的一款兼容MIPS32的处理器核，其主要面向的是数字电视、机顶盒设备、网络设备、存储设备及消费类电子产品市场。该SoC CPU的研制成功标志着我国在微处理器的设计方面实现了重大突破，并且打破了我国长期依赖于外国处理器的现状。但是对于该SoC CPU而言，国内选择使用该款CPU的厂商并不多。而一款CPU要想大规模地推广开来，CPU厂商对其开发工具的支持要足够强大，CPU厂商必须提供稳定地开发工具链。而这其中调试器的作用尤其重要，因为在嵌入式SoC芯片的设计开发过程中，采用一种高效而稳定的调试方案有助于降低芯片的开发难度，能够帮助开发人员快速定位问题所在，从而大大缩短芯片的开发周期。然而国内对SoC CPU的片上调试技术的研究还处于起步阶段，因此本课题的研究意义极大。 本论文首先描述了嵌入式开发中的远程调试的概念，随后又详细介绍了当前嵌入式领域中所采用的各种调试方案：软件仿真调试方案、软件插桩调试方案、ICE调试方案以及片上调试方案。本论文主要研究的是针对该SoC CPU的片上调试方案的实现。因此，深入研究了该SoC CPU的架构特点，SoC CPU对调试异常的处理，调试模式下的内存映射等内容。本文中的SoC CPU采用的是EJTAG来支持其片上调试，片上调试方案实现的基础就是EJTAG接口，所以本论文对EJTAG的工作原理进行了详细的描述。在调试软件的选择上，使用GDB来作为调试主机端的调试器，，进行源码级的调试工作。并在研究了GDB远程调试协议RSP的基础上，实现了一个调试代理，即gdb server，实现了GDB调试器对SoC处理器EJTAG接口的支持，从而实现了一个低成本、支持源码级调试的片上调试方案。
[Abstract]:With the continuous development of integrated circuit technology in China, more and more domestic SoC chips developed by our country appear in the market. The research object of this subject, SoC CPU Core, is a MIPS32 compatible processor core developed by our country, which is mainly aimed at digital TV, set-top box equipment, network equipment, storage equipment and consumer electronic product market. The successful development of the SoC CPU marks a great breakthrough in the design of microprocessors in our country, and breaks the present situation that our country relies on foreign processors for a long time. But for the SoC CPU, there are not many domestic manufacturers who choose to use the CPU. If a CPU is to be popularized on a large scale, the support of CPU vendors for its development tools should be strong enough, and CPU vendors must provide a stable development tool chain. Among them, the debugger plays a particularly important role, because in the process of designing and developing embedded SoC chip, adopting an efficient and stable debugging scheme helps to reduce the difficulty of chip development and can help developers to locate the problem quickly. Thus, the development cycle of the chip is greatly shortened. However, the domestic research on-chip debugging technology of SoC CPU is still in its infancy, so the research of this topic is of great significance. This paper first describes the concept of remote debugging in embedded development, and then introduces in detail all kinds of debugging schemes used in the embedded field: software simulation debugging scheme, software pile debugging scheme, ICE debugging scheme and on-chip debugging scheme. This paper mainly studies the implementation of on-chip debugging scheme for the SoC CPU. Therefore, the architecture characteristics of the SoC CPU are deeply studied, such as the handling of debugging exceptions by, SoC CPU, the memory mapping in debugging mode, and so on. In this paper, SoC CPU uses EJTAG to support on-chip debugging, and the implementation of on-chip debugging scheme is based on EJTAG interface, so the working principle of EJTAG is described in detail in this paper. In the selection of debugging software, GDB is used as the debugger on the debugging host side to debug the source code level. On the basis of studying GDB remote debugging protocol RSP, a debugging agent is implemented, that is, gdb server, realizes the support of GDB debugger for SoC processor EJTAG interface, thus realizing a low cost on-chip debugging scheme which supports source code level debugging.
【学位授予单位】：中国海洋大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN47;TP368.1
本文编号：2482671
[Abstract]:With the continuous development of integrated circuit technology in China, more and more domestic SoC chips developed by our country appear in the market. The research object of this subject, SoC CPU Core, is a MIPS32 compatible processor core developed by our country, which is mainly aimed at digital TV, set-top box equipment, network equipment, storage equipment and consumer electronic product market. The successful development of the SoC CPU marks a great breakthrough in the design of microprocessors in our country, and breaks the present situation that our country relies on foreign processors for a long time. But for the SoC CPU, there are not many domestic manufacturers who choose to use the CPU. If a CPU is to be popularized on a large scale, the support of CPU vendors for its development tools should be strong enough, and CPU vendors must provide a stable development tool chain. Among them, the debugger plays a particularly important role, because in the process of designing and developing embedded SoC chip, adopting an efficient and stable debugging scheme helps to reduce the difficulty of chip development and can help developers to locate the problem quickly. Thus, the development cycle of the chip is greatly shortened. However, the domestic research on-chip debugging technology of SoC CPU is still in its infancy, so the research of this topic is of great significance. This paper first describes the concept of remote debugging in embedded development, and then introduces in detail all kinds of debugging schemes used in the embedded field: software simulation debugging scheme, software pile debugging scheme, ICE debugging scheme and on-chip debugging scheme. This paper mainly studies the implementation of on-chip debugging scheme for the SoC CPU. Therefore, the architecture characteristics of the SoC CPU are deeply studied, such as the handling of debugging exceptions by, SoC CPU, the memory mapping in debugging mode, and so on. In this paper, SoC CPU uses EJTAG to support on-chip debugging, and the implementation of on-chip debugging scheme is based on EJTAG interface, so the working principle of EJTAG is described in detail in this paper. In the selection of debugging software, GDB is used as the debugger on the debugging host side to debug the source code level. On the basis of studying GDB remote debugging protocol RSP, a debugging agent is implemented, that is, gdb server, realizes the support of GDB debugger for SoC processor EJTAG interface, thus realizing a low cost on-chip debugging scheme which supports source code level debugging.
【学位授予单位】：中国海洋大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN47;TP368.1
【参考文献】
相关期刊论文 前4条
1 朱建培;;基于龙芯一号IP核的EJTAG调试[J];单片机与嵌入式系统应用;2008年04期
2 龚兰兰;刘晓升;朱巧明;;远程调试系统的关键技术分析[J];计算机应用与软件;2010年10期
3 雷鸿;汪海;;基于嵌入式处理器的研究[J];软件导刊;2011年08期
4 舒展;;嵌入式系统综述[J];现代计算机(专业版);2011年05期
相关硕士学位论文 前6条
1 龚伟;基于gdb的嵌入式系统调试器的设计与实现[D];电子科技大学;2006年
2 严明;嵌入式微处理器可测性设计与片上调试技术的研究与实现[D];国防科学技术大学;2005年
3 朱梅;基于JTAG标准的通用交叉调试代理的设计和实现[D];电子科技大学;2007年
4 徐宗霖;基于JTAG口的ARM编程器研究与开发[D];浙江工业大学;2007年
5 周智俊;ARM调试系统的研究与实现[D];电子科技大学;2008年
6 王琼;嵌入式Linux软件调试技术研究与实现[D];华中科技大学;2007年
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