基于FPGA的双精度浮点矩阵运算单元设计

发布时间：2019-05-23 03:48

【摘要】：为适应未来信息化战争的需要,导弹武器系统将采用更先进的导航制导控制技术,如多模复合导航制导、更加复杂的误差补偿算法、在多源信号采集处理中广泛采用的数字滤波等等。目前主要依靠通用DSP构建弹上计算机进行相关的信息处理,难以满足多种类高性能计算的要求。若将一些复杂的导航算法在硬件层面上实现,将大大提高导弹导航控制系统的实时性、精度和可靠性。本论文首先查阅相关文献资料,分析研究常用的捷联惯性导航算法,确立了设计双精度浮点矩阵运算IP核的具体方案,并对各个运算模块进行了划分。其次,对浮点运算器设计方法进行了深入研究,根据IEEE754浮点标准,采用Verilog HDL语言在Spartan-6系列FPGA上设计了浮点加、减、乘、除、开方基本浮点运算模块。再次,通过分析研究导航算法的特点,设计出了分布式并行计算的硬件体系结构。本论文创新地设计了一种基于流水线结构的多个浮点运算器并行计算的IP硬件体系结构,在有限的硬件资源上实现了速度和面积的最优。该结构包括一个中心调度模块和十个并行浮点基本运算模块。中心调度模块负责组织控制算法的计算步骤和顺序。外围模块符合IEEE754标准,可同时进行三组加、减、乘、除运算和一组开方运算。并按照AHB总线标准设计了矩阵运算IP接口,用于和SOC内处理器进行数据交互。以此为基础,实现了捷联惯性导航算法的导航计算、四元数矩阵转换和卡尔曼滤波中关键的矩阵求逆。最后在赛灵思的FPGA芯片上验证以上IP设计,并与C6713B DSP开发板上三种算法的运行速度和计算精度作比较。实验表明,在计算精度一致的同时,IP核的运算速度要大大高于DSP,大约是其10倍以上。
[Abstract]:In order to meet the needs of future information warfare, the missile weapon system will adopt more advanced navigation guidance and control technology, such as multi-mode composite navigation guidance, more complex error compensation algorithm. Digital filtering is widely used in multi-source signal acquisition and processing. At present, it is difficult to meet the requirements of many kinds of high performance computing by relying on the general DSP to construct the pop-up computer for related information processing. If some complex navigation algorithms are implemented at the hardware level, the real-time, accuracy and reliability of the missile navigation control system will be greatly improved. First of all, this paper refers to the relevant literature, analyzes and studies the commonly used strapdown inertial navigation algorithm, establishes the specific scheme of designing double-precision floating-point matrix operation IP kernel, and divides each operation module. Secondly, the design method of floating-point operator is deeply studied. According to IEEE754 floating-point standard, the basic floating-point operation module of floating-point addition, subtraction, multiplication, division and square is designed on Spartan-6 series FPGA by using Verilog HDL language. Thirdly, the hardware architecture of distributed parallel computing is designed by analyzing and studying the characteristics of navigation algorithm. In this paper, a IP hardware architecture based on pipeline architecture for parallel computing of multiple floating-point operators is designed innovatively, and the optimization of speed and area is realized in terms of limited hardware resources. The structure includes a central scheduling module and ten parallel floating-point basic operation modules. The central scheduling module is responsible for organizing the calculation steps and sequence of the control algorithm. The peripheral module conforms to IEEE754 standard and can carry out three groups of addition, subtraction, multiplication, division and a set of square operations at the same time. According to AHB bus standard, the IP interface of matrix operation is designed, which is used to interact with SOC internal processor. On this basis, the navigation calculation of strapdown inertial navigation algorithm, quaternion matrix transformation and the key matrix inversion in Kalman filtering are realized. Finally, the above IP design is verified on the FPGA chip of Cylinth, and the running speed and calculation accuracy of the three algorithms on the C6713B DSP development board are compared. The experimental results show that while the calculation accuracy is the same, the operation speed of IP kernel is much higher than that of DSP, is about 10 times higher than that of DSP,.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.2

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