支持可重构的流接口的设计与实现
发布时间：2019-05-23 09:24
【摘要】：可重构计算通过在时空域上重用硬件资源完成计算任务,在可重构系统中,硬件任务可以像软件程序一样动态的调用和修改,既保留了硬件的计算性能,又具备了软件的灵活性。随着以图像处理、数字信号处理为代表的数据流计算应用日趋广泛,如何使得编程人员根据具体的应用需求动态配置相应的功能,并通过不同类型的并行性发掘、兼顾数据流处理的高效能和配置灵活性,是目前可重构系统面临的两个主要问题。 针对上述问题,本文以面向数据流的硬件任务接口设计、可重构流处理结构设计为出发点,完成了以下研究工作： 1、针对数据流处理,设计并实现了基于总线的统一的流接口。利用数据流驱动计算特征,为用户硬件任务提供基于总线的统一的流接口以及对应的编程API(Application Programming Interface)。上述接口设计支持硬件任务的高性能处理,还对系统编程人员屏蔽底层设计细节,便于实现硬件任务的统一管理和灵活调度。 2、针对基于总线的流接口存在的带宽瓶颈、CPU占用率高等不足,设计并实现了基于LocalLink的统一的流接口。该接口利用同步的、点对点的数据流通信接口协议,使得数据流通信连接关系可根据任务之间的数据依赖关系进行动态配置,克服了传统片上系统总线的通信瓶颈,并能够显著降低CPU利用率。经测试,硬件任务与软件任务之间的通信带宽可达到800Mbps,硬件任务与硬件任务之间的通信带宽可达到800Mbps。 3、以FPGA为数据流处理平台,设计并实现了功能和互连可动态重构的高效能片上系统(System-on-Chip, SoC)。通过部分动态重构技术实现功能重构,通过交叉开关矩阵实现任务间互连关系重构,从而灵活地支持多种数据流计算模式,发掘不同种类的并行。实验结果表明,与已有基于FPGA的片上系统实现相比,AES、DES、DCT处理功耗效能有显著提升,该结构便于用户根据应用需要配置相应的数据流计算模式,降低了设计难度,并充分发挥了可重构系统的高效性和灵活性。
[Abstract]:Reconfigurable computing completes computing tasks by reusing hardware resources in space-time domain. In reconfigurable systems, hardware tasks can be called and modified as dynamically as software programs, which not only preserves the computing performance of hardware. It also has the flexibility of software. With the increasing application of data stream computing represented by image processing and digital signal processing, how to make programmers dynamically configure the corresponding functions according to the specific application requirements, and through different types of parallelism mining, Taking into account the high efficiency and configuration flexibility of data flow processing are the two main problems faced by reconfigurable systems at present. In order to solve the above problems, this paper takes the design of data flow oriented hardware task interface and restructured flow processing structure as the starting point, and completes the following research work: 1, for data flow processing, A unified flow interface based on bus is designed and implemented. Using data flow driven computing characteristics to provide a unified bus-based flow interface for user hardware tasks and the corresponding programming API (Application Programming Interface). The above interface design supports the high performance processing of hardware tasks, and also shielded the underlying design details for system programmers, which is convenient to realize the unified management and flexible scheduling of hardware tasks. 2. Aiming at the bandwidth bottleneck of bus-based stream interface and the high utilization rate of CPU, a unified flow interface based on LocalLink is designed and implemented. The interface makes use of the synchronous, point-to-point data flow communication interface protocol, so that the data flow communication connection relationship can be dynamically configured according to the data dependence between tasks, and the communication bottleneck of the traditional system bus on the chip is overcome. It can significantly reduce the utilization rate of CPU. After testing, the communication bandwidth between hardware task and software task can reach 800Mbps, and the communication bandwidth between hardware task and hardware task can reach 800Mbps. 3. Using FPGA as the data flow processing platform, an efficient energy-on-chip system (System-on-Chip, SoC).) with dynamic refactoring function and interconnection is designed and implemented. The functional reconstruction is realized by partial dynamic reconstruction technology, and the interconnection relationship between tasks is reconstructed by cross-switching matrix, so as to flexibly support a variety of data flow computing patterns and discover different kinds of parallelism. The experimental results show that compared with the existing on-chip system implementation based on FPGA, the power consumption efficiency of AES,DES,DCT processing is significantly improved. The structure is convenient for users to configure the corresponding data flow calculation mode according to the application needs, and reduces the design difficulty. The efficiency and flexibility of the reconfigurable system are brought into full play.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7
本文编号：2483784
[Abstract]:Reconfigurable computing completes computing tasks by reusing hardware resources in space-time domain. In reconfigurable systems, hardware tasks can be called and modified as dynamically as software programs, which not only preserves the computing performance of hardware. It also has the flexibility of software. With the increasing application of data stream computing represented by image processing and digital signal processing, how to make programmers dynamically configure the corresponding functions according to the specific application requirements, and through different types of parallelism mining, Taking into account the high efficiency and configuration flexibility of data flow processing are the two main problems faced by reconfigurable systems at present. In order to solve the above problems, this paper takes the design of data flow oriented hardware task interface and restructured flow processing structure as the starting point, and completes the following research work: 1, for data flow processing, A unified flow interface based on bus is designed and implemented. Using data flow driven computing characteristics to provide a unified bus-based flow interface for user hardware tasks and the corresponding programming API (Application Programming Interface). The above interface design supports the high performance processing of hardware tasks, and also shielded the underlying design details for system programmers, which is convenient to realize the unified management and flexible scheduling of hardware tasks. 2. Aiming at the bandwidth bottleneck of bus-based stream interface and the high utilization rate of CPU, a unified flow interface based on LocalLink is designed and implemented. The interface makes use of the synchronous, point-to-point data flow communication interface protocol, so that the data flow communication connection relationship can be dynamically configured according to the data dependence between tasks, and the communication bottleneck of the traditional system bus on the chip is overcome. It can significantly reduce the utilization rate of CPU. After testing, the communication bandwidth between hardware task and software task can reach 800Mbps, and the communication bandwidth between hardware task and hardware task can reach 800Mbps. 3. Using FPGA as the data flow processing platform, an efficient energy-on-chip system (System-on-Chip, SoC).) with dynamic refactoring function and interconnection is designed and implemented. The functional reconstruction is realized by partial dynamic reconstruction technology, and the interconnection relationship between tasks is reconstructed by cross-switching matrix, so as to flexibly support a variety of data flow computing patterns and discover different kinds of parallelism. The experimental results show that compared with the existing on-chip system implementation based on FPGA, the power consumption efficiency of AES,DES,DCT processing is significantly improved. The structure is convenient for users to configure the corresponding data flow calculation mode according to the application needs, and reduces the design difficulty. The efficiency and flexibility of the reconfigurable system are brought into full play.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7
【共引文献】
相关期刊论文 前2条
1 孙兆伟;刘源;邢雷;徐国栋;;面向多任务的可重构星载计算机设计[J];系统工程与电子技术;2011年06期
2 陈乃金;江建慧;陈昕;周洲;徐莹;潘诚;;动态可重构系统的时域划分及其行为级算法的定量分析[J];小型微型计算机系统;2011年02期
，本文编号：2483784
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