基于FPGA单指令浮点乘法自主控制器设计

发布时间：2019-05-25 00:45

【摘要】：为实现一种多浮点操作数乘法运算的自主运算控制器,提出了一种基于FPGA并行操作的硬连接电路的多浮点数乘法运算控制器及其时序控制的方法,该控制器对一条多浮点操作数乘法运算指令的命令字和多浮点操作数连续写入并存储,在内部时序脉冲作用下,可以自主完成读出浮点操作数执行乘法运算,写入存储多浮点操作数过程与执行乘法运算命令的过程能够并行进行;在控制器执行乘法运算命令过程中,系统可以读出执行命令过程中的中间结果和最终运算结果;论述了该控制器的电路构成和基本原理,分析命令字与多操作数在内部时序脉冲作用下的执行过程,应用Verilog HDL语言实现相关硬件的构建和连接;设计完成后通过仿真测试可知,该控制器运行的最高频率为250MHz,从输入到输出端口最小延时是3.185ns,最大延时是15.336ns,且能够自主完成浮点数乘法运算。
[Abstract]:In order to realize an autonomous operation controller for multi-floating-point operands multiplication, a multi-floating-point multiplication controller based on FPGA parallel operation and its timing control method are proposed. The controller continuously writes and stores the command word and the multi-floating-point operands of a multi-floating-point operands multiplication instruction, and under the action of the internal timing pulse, it can independently complete the multiplication operation of the readout floating-point operands. The process of writing and storing multi-floating-point operands can be carried out in parallel with the process of executing multiplication commands. In the process of executing the multiplication command by the controller, the system can read the intermediate result and the final operation result in the process of executing the command. The circuit structure and basic principle of the controller are discussed, the execution process of command word and multi-operands under the action of internal sequential pulse is analyzed, and the related hardware is constructed and connected by Verilog HDL language. After the design is completed, the simulation results show that the maximum frequency of the controller is 250MHz, the minimum delay from input to output port is 3.185ns, the maximum delay is 15.336ns, and the floating-point multiplication operation can be completed independently.
【作者单位】：广西科技大学电气与信息工程学院;
【基金】：广西科学基金项目(桂科自2011GXNSFA018153)
【分类号】：TP332

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