两端口EHCI设计及内嵌模式下API接口的实现

发布时间：2019-05-28 01:38

【摘要】：EHCI(Enhanced Host Controller,加强的主机控制接口)是USB(Universal Serial Bus,通用串行接口)2.0版本协议下的国际标准主机接口,在市场上得到了广泛的应用。本次研究的主要目的有三个,一是通过Verilog硬件设计语言,设计出一版传输速度更快且无限接近理论值480Mb/s的EHCI,并且RTL代码是可综合的;二是要实现两个线上传输接口;三是在设计中添加额外的寄存器,然后在使用到这些寄存器基础上用C语言设计API(Application Programming Interface,应用程序编程接口)接口,通过使用API接口,系统可以在不使用标准EHCI驱动的情形下,控制EHCI做传输。本次研究的第一步工作是架构规划,在论文中系统的描述了如何根据设计的目标计算出设计中重要参数的方法,这些参数包含FIFO的大小,pipe-line深度等重要参数,在确定了参数之后,规划各个模块的功能及实现方式,例如各个模块所在的时钟领域,模块与模块之间如何协调工作,以及穿频问题的处理方式。之后就是根据之前的规划实现RTL代码的工作,在实现RTL代码的时候,需要严格遵守代码风格,确保代码可以被综合成网表。然后就是仿真验证,此次仿真的环境是采用UVM(Universal Verification Methodology,通用验证方法)验证方法学实现的,测试内容全面,效率高。在仿真工作即将结束的时候,同步进行了FPGA测试和API接口代码的实现,并且将API接口的代码在FPGA上进行了测试。最后一步就是在仿真环境中测试EHCI的传输速度,以及通过综合代码,确定EHCI的面积大小。通过本次设计,可以确认的是,实际上EHCI的传输速度最快能够达到416Mb/s,已经比较接近理论值480Mb/s,市面上测试到的EHCI的速度最快就300Mb/s左右。能够达到这样的传输速度需要两个前提条件,一是驱动程序尽量不将没有用处的传输控制包排入传输列表中,并且每次传输的传输量尽量达到最大值。另一方面是与之进行对等传输设备要够快,才能体现出主机EHCI的速度优势。速度的提升带来的一个影响就是面积的增大,通过合成得到的结果来看,与过去旧的一些版本的EHCI相比,面积提升了一倍。假设市面上的EHCI是在速度和面积之间选择的一个比较合理的平衡点,本次设计就是抛开这个平衡点追求速度,结果就是速度提升了30%,面积增加了100%.
[Abstract]:EHCI (Enhanced Host Controller, enhanced host control interface is an international standard host interface under USB (Universal Serial Bus, version 2.0 protocol, which has been widely used in the market. There are three main purposes of this study. One is to design a version of EHCI, with faster transmission speed and infinitely close to the theoretical value 480Mb/s through Verilog hardware design language, and the other is to realize two on-line transmission interfaces. The third is to add additional registers to the design, and then design the API (Application Programming Interface, application programming interface with C language on the basis of using these registers) interface, by using API interface, The system can control EHCI transmission without using standard EHCI driver. The first step of this study is architecture planning. In this paper, we systematically describe how to calculate the important parameters in the design according to the design objectives, including the size of FIFO, the depth of pipe-line and other important parameters. After determining the parameters, the function and implementation of each module are planned, such as the clock field in which each module is located, how to coordinate between modules, and how to deal with the problem of penetration frequency. Then, according to the previous planning to implement RTL code, in the implementation of RTL code, we need to strictly abide by the code style to ensure that the code can be integrated into a network table. Then it is verified by simulation, the environment of this simulation is realized by UVM (Universal Verification Methodology, general verification method), the test content is comprehensive and the efficiency is high. At the end of the simulation work, the FPGA test and the implementation of API interface code are carried out synchronously, and the code of API interface is tested on FPGA. The last step is to test the transmission speed of EHCI in the simulation environment and to determine the area of EHCI by synthesizing the code. Through this design, it can be confirmed that in fact, the transmission speed of EHCI can reach 416MB / s, which is close to the theoretical value of 480MB / s, and the speed of EHCI tested on the market is about 300Mb/s. There are two prerequisites for achieving such a transmission speed. One is that the driver does not put useless transmission control packets into the transmission list as far as possible, and the transmission volume of each transmission reaches the maximum value as much as possible. On the other hand, it is necessary to carry out peer-to-peer transmission equipment fast enough to reflect the speed advantage of host EHCI. One of the effects of the increase in speed is the increase in area, which is twice as large as that of some old versions of EHCI. Assuming that the EHCI on the market is a reasonable equilibrium point between speed and area, this design is to put aside the pursuit speed of this equilibrium point, and the result is that the speed is increased by 30% and the area is increased by 100%.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP334.7

【共引文献】