RISC处理器中IMMU的设计与实现
发布时间：2019-05-28 19:58
【摘要】：IMMU (Instruction Memory Management Unit)指令存储管理单元,是微处理器的一个重要组成部分。其作用在于完成从虚拟地址(virtual address)到物理地址(phusical address)的转换,对存储空间进行分配,对存储信息进行保护,从而保证操作系统的有效运行。随着大数据时代的到来,高通量计算系统越来越受到相关研究人员的关注。在这样的背景下,作为微处理器的重要组成部分,IMMU需要不断提高其有效操作的速度,减少器件运行中的功耗,同时,在保证IMMU性能的前提下,减少器件面积。针对以上问题,笔者对RISC(Reduced Instruction Set Computing)架构下处理器中的IMMU进行了相关研究,主要工作安排如下： 1.分析RISC架构下,IMMU的设计原理、存储管理机制及快速地址访问技术。针对IMMU设计的特点及存在的问题,同时,借鉴市场表现出色的处理器产品,完成对IMMU的方案设计。该IMMU支持多线程和流水级操作,其重要的组成部件包括ITLB(Instrution Translation Lookaside Buffer)和Hardware Translation Table Walk。这样的设计架构,能够有效地减少IMMU运行功耗,同时,提高器件完成有效操作的速度； 2. IMMU器件的工程设计与实现。在ITLB设计中,对SRAM的设计方案进行了改进,提高了ITLB器件的读写速度；Hardware Translation Table Walk采用硬件电路方式实现,支持不同粒度的地址访问。器件内部建立了完善的控制系统有效地避免了器件运行中的冲突问题,借助改进型的轮询机制设计方法,设计出IMMU与其他器件之间的通信接口电路,在提高微处理器各器件之间的协调能力的前提下提升了IMMU的整体性能； 3. IMMU器件的仿真与验证。一方面,利用synopsys设计软件对IMMU器件进行寄存器传输级和网表级的逻辑验证；另一方面,利用Xilinx XC7K325T FPGA芯片,进行FPGA原型验证； 4. IMMU器件的性能评估。针对IMMU器件的工作频率、面积和功耗等重要问题,分别从时序、面积和功耗三个角度,完成对设计器件性能的评估；本课题中,在65nm制造工艺下,IMMU器件能够达到800MHz,与相同工艺水平的处理器芯片相比,该设计综合面积占芯片总面积的0.75%,功耗占芯片总功耗的3.33%,结果比较可观。因此,本课题研究工作对IMMU的设计工作具有很好的现实指导意义。
[Abstract]:IMMU (Instruction Memory Management Unit) instruction storage management unit is an important part of microprocessor. Its function is to complete the conversion from virtual address (virtual address) to physical address (phusical address), allocate storage space and protect storage information, so as to ensure the effective operation of the operating system. With the advent of big data era, high-throughput computing system has been paid more and more attention by relevant researchers. In this context, as an important part of microprocessor, IMMU needs to improve the speed of its effective operation, reduce the power consumption in the operation of the device, and reduce the device area under the premise of ensuring the performance of IMMU. In view of the above problems, the author has carried on the related research to the IMMU in the RISC (Reduced Instruction Set Computing) architecture, the main work arrangement is as follows: 1. The design principle, storage management mechanism and fast address access technology of IMMU under RISC architecture are analyzed. According to the characteristics and existing problems of IMMU design, the scheme design of IMMU is completed by drawing lessons from the processor products with excellent market performance. The IMMU supports multithreading and flow-level operations, and its important components include ITLB (Instrution Translation Lookaside Buffer) and Hardware Translation Table Walk. Such a design architecture can effectively reduce the power consumption of IMMU, at the same time, improve the speed of the device to complete the effective operation; 2. Engineering design and implementation of IMMU devices. In the design of ITLB, the design scheme of SRAM is improved, and the reading and writing speed of ITLB device is improved.; Hardware Translation Table Walk is realized by hardware circuit and supports address access with different granularity. A perfect control system is established to effectively avoid the conflict in the operation of the device. With the help of the improved polling mechanism design method, the communication interface circuit between IMMU and other devices is designed. On the premise of improving the coordination ability of each device of the microprocessor, the overall performance of IMMU is improved. 3. Simulation and verification of IMMU devices. On the one hand, using synopsys design software to verify the register transmission level and network table level of IMMU devices; on the other hand, using Xilinx XC7K325T FPGA chip to verify the FPGA prototype; 4. Performance evaluation of IMMU devices. Aiming at the important problems such as working frequency, area and power consumption of IMMU devices, the performance of the designed devices is evaluated from three aspects: timing, area and power consumption. In this paper, under the 65nm manufacturing process, the IMMU device can reach 800MHz. Compared with the processor chip at the same process level, the comprehensive area of the design accounts for 0.75% of the total chip area and the power consumption accounts for 3.33% of the total power consumption of the chip. The results are considerable. Therefore, the research work of this subject has a good practical guiding significance for the design of IMMU.
【学位授予单位】：武汉理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
[Abstract]:IMMU (Instruction Memory Management Unit) instruction storage management unit is an important part of microprocessor. Its function is to complete the conversion from virtual address (virtual address) to physical address (phusical address), allocate storage space and protect storage information, so as to ensure the effective operation of the operating system. With the advent of big data era, high-throughput computing system has been paid more and more attention by relevant researchers. In this context, as an important part of microprocessor, IMMU needs to improve the speed of its effective operation, reduce the power consumption in the operation of the device, and reduce the device area under the premise of ensuring the performance of IMMU. In view of the above problems, the author has carried on the related research to the IMMU in the RISC (Reduced Instruction Set Computing) architecture, the main work arrangement is as follows: 1. The design principle, storage management mechanism and fast address access technology of IMMU under RISC architecture are analyzed. According to the characteristics and existing problems of IMMU design, the scheme design of IMMU is completed by drawing lessons from the processor products with excellent market performance. The IMMU supports multithreading and flow-level operations, and its important components include ITLB (Instrution Translation Lookaside Buffer) and Hardware Translation Table Walk. Such a design architecture can effectively reduce the power consumption of IMMU, at the same time, improve the speed of the device to complete the effective operation; 2. Engineering design and implementation of IMMU devices. In the design of ITLB, the design scheme of SRAM is improved, and the reading and writing speed of ITLB device is improved.; Hardware Translation Table Walk is realized by hardware circuit and supports address access with different granularity. A perfect control system is established to effectively avoid the conflict in the operation of the device. With the help of the improved polling mechanism design method, the communication interface circuit between IMMU and other devices is designed. On the premise of improving the coordination ability of each device of the microprocessor, the overall performance of IMMU is improved. 3. Simulation and verification of IMMU devices. On the one hand, using synopsys design software to verify the register transmission level and network table level of IMMU devices; on the other hand, using Xilinx XC7K325T FPGA chip to verify the FPGA prototype; 4. Performance evaluation of IMMU devices. Aiming at the important problems such as working frequency, area and power consumption of IMMU devices, the performance of the designed devices is evaluated from three aspects: timing, area and power consumption. In this paper, under the 65nm manufacturing process, the IMMU device can reach 800MHz. Compared with the processor chip at the same process level, the comprehensive area of the design accounts for 0.75% of the total chip area and the power consumption accounts for 3.33% of the total power consumption of the chip. The results are considerable. Therefore, the research work of this subject has a good practical guiding significance for the design of IMMU.
【学位授予单位】：武汉理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
【共引文献】
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