基于SOPC的2D-FFT处理器的设计与实现
发布时间：2019-06-02 11:03
【摘要】：快速傅里叶变换广泛地应用于数字信号处理(DSP),尤其是二维快速傅里叶变换(2D-FFT)在成像技术的光谱和频域分析中有重要的应用,如图像数字水印、指纹识别、合成孔径雷达成像处理以及医学成像等。随着所需处理的数字信号量的增加,对2D-FFT性能和实时性的要求也越来越高。目前2D-FFT算法的实现多局限于专用集成电路与DSP,但这两种实现方式都存在着某种不足。当前,为满足应用需求,弥补前两种实现方式的不足,采用速度更快、重构性好的FPGA实现具有并行特征的2D-FFT算法,己成为国内外研究的热点。 本设计追逐热点研究,探索在FPGA上实现高性能的2D-FFT处理器,并将所设计的2D-FFT处理单元封装成IP核,采用自定义组件的方式添加进SOPC系统中,并添加相关的系统组件如Nios Ⅱ软核、SDRAM等来实现一个可裁剪、可扩充、可升级的2D-FFT处理系统。在FPGA底层设计中,采用蝶形单元与CORDIC算法设计实现FFT处理单元,并采用乒乓倒换的方式实现矩阵转置,再用这两个关键模块组合成所需的2D-FFT处理模块,参照最新Avalon总线标准对其进行模块封装以利于采用自定义组件方法集成进SOPC系统。 该系统在Quartus Ⅱ8.0开发平台中进行最终的布局布线,经过专业仿真工且ModelSim进行仿真和测试后,下载到Altera公司的所提供的开发板DE2上进行实物验证。并将最终实物验证结果与Matlab函数处理结果来对比,最后结果表明本设计具有运行稳定,速度快,占用资源少等优点,具有很好的应用前景。
[Abstract]:Fast Fourier transform is widely used in digital signal processing (DSP), especially two-dimensional fast Fourier transform (2D-FFT), which has important applications in spectral and frequency domain analysis of imaging technology, such as image digital watermarking, fingerprint recognition. Synthetic aperture radar imaging processing and medical imaging. With the increase of digital semaphores to be processed, the performance and real-time requirements of 2D-FFT are getting higher and higher. At present, the implementation of 2D-FFT algorithm is mostly limited to ASIC and DSP, but there are some shortcomings in these two implementation methods. At present, in order to meet the application requirements and make up for the shortcomings of the first two implementation methods, the implementation of 2D-FFT algorithm with parallel characteristics by using FPGA with faster speed and good reconstruction has become a hot research topic at home and abroad. This design pursues the hot research, explores the implementation of high performance 2D-FFT processor on FPGA, and encapsulates the designed 2D-FFT processing unit into IP core, which is added to the SOPC system by means of custom components. The related system components such as Nios II soft core, SDRAM and so on are added to realize a clipped, extensible and upgraded 2D-FFT processing system. In the bottom design of FPGA, the butterfly element and CORDIC algorithm are used to design and implement the FFT processing unit, and the ping-pong switching method is used to realize the matrix transposition, and then the two key modules are combined into the required 2D-FFT processing module. According to the latest Avalon bus standard, the module encapsulation is carried out to facilitate the integration of custom component method into SOPC system. The final layout and routing of the system is carried out in Quartus 鈪，
本文编号：2491044
[Abstract]:Fast Fourier transform is widely used in digital signal processing (DSP), especially two-dimensional fast Fourier transform (2D-FFT), which has important applications in spectral and frequency domain analysis of imaging technology, such as image digital watermarking, fingerprint recognition. Synthetic aperture radar imaging processing and medical imaging. With the increase of digital semaphores to be processed, the performance and real-time requirements of 2D-FFT are getting higher and higher. At present, the implementation of 2D-FFT algorithm is mostly limited to ASIC and DSP, but there are some shortcomings in these two implementation methods. At present, in order to meet the application requirements and make up for the shortcomings of the first two implementation methods, the implementation of 2D-FFT algorithm with parallel characteristics by using FPGA with faster speed and good reconstruction has become a hot research topic at home and abroad. This design pursues the hot research, explores the implementation of high performance 2D-FFT processor on FPGA, and encapsulates the designed 2D-FFT processing unit into IP core, which is added to the SOPC system by means of custom components. The related system components such as Nios II soft core, SDRAM and so on are added to realize a clipped, extensible and upgraded 2D-FFT processing system. In the bottom design of FPGA, the butterfly element and CORDIC algorithm are used to design and implement the FFT processing unit, and the ping-pong switching method is used to realize the matrix transposition, and then the two key modules are combined into the required 2D-FFT processing module. According to the latest Avalon bus standard, the module encapsulation is carried out to facilitate the integration of custom component method into SOPC system. The final layout and routing of the system is carried out in Quartus 鈪，
本文编号：2491044
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