PowerPC处理器整数运算单元的设计与实现

发布时间：2019-06-03 11:13

【摘要】：本文研究的是基于PowerPC体系结构超标量X型微处理器中的整数运算单元。整数运算单元是X型微处理器的核心单元，承担起整个芯片关于整数的加法、乘法、除法和逻辑的运算。因而对整数运算单元的研究与设计有相当重要的意义。本文重点研究和设计整数运算单元的加法器、乘法器和除法器。加法器采用的是改进型超前进位加法器的设计，采用组内串行进位，组间并行求得进位的方法，实现了两个32位整数的相加，并对进位和求和‖的电路进行了优化；乘法器采用的是改进型的Booth编码乘法器设计，采用的是基为4的Booth编码，并对产生的部分积，采用改进型的华莱士树进行压缩，并采用反馈电路将每个周期得到的部分积迭代相加，极大加快了运算的速度，优化了电路；除法器采用的是基为4的不恢复余数除法器设计，每个周期处理整数的两位相除，通过20个周期循环完成两位32位整数的除法，在求商‖的电路实现上进行了适当的优化，加快了异号相除得到的商的修正运算，在整个除法的电路上，采用循环电路的设计，虽然增加了运算时间，但节省了大量面积和成本。本文最后，对整数运算单元的加法器、除法器和乘法器，，进行了模块级和系统级的验证，经过对比验证，所设计的部分，通过了前仿和后仿，在论文的第五章，给出了最终得到的设计版图。
[Abstract]:In this paper, the integer operation unit in superscalar X microprocessor based on PowerPC architecture is studied. Integer operation unit is the core unit of type X microprocessor, which undertakes the addition, multiplication, division and logic operation of integer in the whole chip. Therefore, it is of great significance to study and design integer operation units. In this paper, the adders, multiplier and divider of integer operation unit are studied and designed. The additive adopts the design of the improved advanced carry adder, adopts the method of serial carry in the group and gets the carry in parallel between the two groups, realizes the addition of two 32-bit integers, and optimizes the circuit of carry sum and sum. The multiplier adopts the improved Booth coding multiplier design, uses the base 4 Booth coding, and uses the improved Wallace tree to compress the generated partial product. The feedback circuit is used to add the partial product of each cycle, which greatly accelerates the operation speed and optimizes the circuit. The divider adopts the design of non-recovery remainder divider based on 4, which processes the division of two bits of integers in each cycle, and completes the division of two-bit 32-bit integers through 20 cycle cycles. The circuit realization of the quotient is properly optimized. The correction operation of quotient obtained by different sign division is speeded up. In the whole division circuit, the design of cyclic circuit is adopted, although the operation time is increased, but a lot of area and cost are saved. At the end of this paper, the adders, dividers and multiplier of integer operation unit are verified at module level and system level. after comparison and verification, the designed part passes through front imitation and post imitation, in the fifth chapter of the paper, The final design layout is given.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332.2;TN402

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