一种缓解多线程访存干扰的VRB内存机制
发布时间：2019-06-12 02:45
【摘要】：目前处理器通过持续增加核数和同时执行的线程数来提高系统性能.但是,增加共享内存的处理器核数和线程数会使得存储器中的行缓存(row-buffer,RB)命中率下降,造成存储器访问功耗增加和访存延迟增加.设计并开发了一种细粒度的victim row-buffer(VRB)内存机制系统来解决此问题.VRB机制提供附加的行缓存(VRB),暂时缓存由于行缓存(RB)冲突而从行缓存(RB)逐出的数据,以备后续可能的访问.这种机制缓解了多线程冲突,增加了DRAM中行缓存数据的重用率,避免了不必要的内存数据阵列的访问、行激活和预充电、数据传输等电路动作,可以通过少量的硬件代价提高内存系统的性能,并节约系统的功耗消耗.通过时序精确的全系统模拟器实验,对比8核的Intel Xeon处理器,所提出的VRB机制可以达到最高17.6%(平均8.7%)的系统级吞吐率改善、最高142.9%(平均51.4%)的行缓存命中率改善以及最高17.6%(平均9.2%)的系统功耗改善.
[Abstract]:At present, the processor improves the system performance by continuously increasing the number of cores and the number of threads executed at the same time. However, increasing the number of processor cores and threads in shared memory will reduce the hit ratio of row cache (row-buffer,RB) in memory, resulting in the increase of memory access power consumption and memory access delay. A fine-granularity victim row-buffer (VRB) memory mechanism system is designed and developed to solve this problem. VRB mechanism provides additional row cache (VRB), temporary cache of data expelled from row cache (RB) due to row cache (RB) conflict for possible subsequent access. This mechanism alleviates multi-thread conflict, increases the reuse rate of row cache data in DRAM, avoids unnecessary access to memory data array, row activation and precharging, data transmission and other circuit actions, can improve the performance of memory system through a small amount of hardware cost, and save the power consumption of the system. Through the experiment of the whole system simulator with accurate timing, compared with the 8-core Intel Xeon processor, the proposed VRB mechanism can improve the system throughput by 17.6% (average 8.7%), the row cache hit ratio by 142.9% (average 51.4%) and the system power consumption by 17.6% (average 9.2%).
【作者单位】： 计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院大学;北京市移动计算和新型终端重点实验室(中国科学院计算技术研究所);
【基金】：国家“九七三”重点基础研究发展计划基金项目(2011CB302501) 国家自然科学基金项目(61020106002,61221062) NSFC与香港RGC合作项目(61161160566) “核高基”国家科技重大专项基金项目(2013ZX0102-8001-001-001)
【分类号】：TP333
，
本文编号：2497663
[Abstract]:At present, the processor improves the system performance by continuously increasing the number of cores and the number of threads executed at the same time. However, increasing the number of processor cores and threads in shared memory will reduce the hit ratio of row cache (row-buffer,RB) in memory, resulting in the increase of memory access power consumption and memory access delay. A fine-granularity victim row-buffer (VRB) memory mechanism system is designed and developed to solve this problem. VRB mechanism provides additional row cache (VRB), temporary cache of data expelled from row cache (RB) due to row cache (RB) conflict for possible subsequent access. This mechanism alleviates multi-thread conflict, increases the reuse rate of row cache data in DRAM, avoids unnecessary access to memory data array, row activation and precharging, data transmission and other circuit actions, can improve the performance of memory system through a small amount of hardware cost, and save the power consumption of the system. Through the experiment of the whole system simulator with accurate timing, compared with the 8-core Intel Xeon processor, the proposed VRB mechanism can improve the system throughput by 17.6% (average 8.7%), the row cache hit ratio by 142.9% (average 51.4%) and the system power consumption by 17.6% (average 9.2%).
【作者单位】： 计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院大学;北京市移动计算和新型终端重点实验室(中国科学院计算技术研究所);
【基金】：国家“九七三”重点基础研究发展计划基金项目(2011CB302501) 国家自然科学基金项目(61020106002,61221062) NSFC与香港RGC合作项目(61161160566) “核高基”国家科技重大专项基金项目(2013ZX0102-8001-001-001)
【分类号】：TP333
，
本文编号：2497663
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