OpenRISC处理器寄存器级仿真与实现
发布时间：2019-06-19 06:21
【摘要】：片上系统（SoC）功能的不断增强，设计复杂度和难度的不断增加以及产品上市周期的日益缩短，使得处理器仿真技术得到了越来越多的重视。处理器仿真不仅在硬件设计阶段可作为处理器功能验证的参照模型发挥重大作用，而且在软件设计阶段可作为软件开发环境中的系统支撑平台而具有重大意义。为了推动开源OpenRISC处理器技术的发展，验证基于SystemC仿真语言进行处理器仿真的优点，本文使用SystemC对开源OpenRISC处理器进行了仿真，给出了OpenRISC处理器最小系统的仿真实现，并重点介绍了OpenRISC流水线仿真设计与实现，可为基于SystemC的OpenRISC处理器的进一步仿真和开发奠定基础。 本文的研究工作主要包括： 首先对处理器仿真技术和SystemC硬件仿真平台进行了分析；详细介绍了处理器仿真技术中的指令集仿真技术和结构仿真技术的功能特点，SystenC硬件仿真平台下的设计方法学、仿真内核和进程的特点和功能。 其次，分析了OpenRISC1200处理器核的结构框架，并通过对额外单元的裁剪给出了最小系统；最小系统包括整数流水单元、寄存器单元和内存；分析了流水线各级的作用，各级中可能发生的冒险，发生冒险的条件以及各种冒险的解决方案。介绍了OpenRISC为匹配主存与CPU性能差异采用的Cache技术的特点；还对OpenRISC指令集的特点分析和分类。 然后，采用SystemC对OpenRISC处理器流水线进行了仿真设计，给出了OpenRISC处理器整体设计框架；实现了流水线中IF级的genpc模块的仿真，ID级的control模块和rf模块的仿真，，EXE级的operandmuxes模块和alu模块的仿真，MA级的lsu模块的仿真和WB级中的wbmux模块的仿真；同时给出了Cache的仿真实现。 最后结合SystemC仿真开发平台，对其进行必要的初始化工作后；针对数据冒险、流水线阻塞、流水线综合性能和Cache功能分别设计了相应的测试用例，给出了其中相关的代码及执行结果；理论分析和实验结果都表明基于仿真语言SystemC对OpenRISC处理器核的仿真是可行的，可在此基础上继续开发和完善并将其用于支持基于OpenRISC的软硬件系统的开发设计。
[Abstract]:With the increasing function of on-chip system (SoC), the increasing complexity and difficulty of design and the shortening of product marketing cycle, more and more attention has been paid to processor simulation technology. Processor simulation can not only play an important role in the hardware design phase as a reference model for processor function verification, but also play an important role in the software design phase as a system support platform in the software development environment. In order to promote the development of open source OpenRISC processor technology and verify the advantages of processor simulation based on SystemC simulation language, this paper uses SystemC to simulate open source OpenRISC processor, gives the simulation implementation of OpenRISC processor minimum system, and focuses on the design and implementation of OpenRISC pipeline simulation, which can lay a foundation for the further simulation and development of OpenRISC processor based on SystemC. The research work of this paper mainly includes: firstly, the processor simulation technology and SystemC hardware simulation platform are analyzed, and the functional characteristics of instruction set simulation technology and structure simulation technology in processor simulation technology, the design methodology under SystenC hardware simulation platform, the characteristics and functions of simulation kernel and process are introduced in detail. Secondly, the structure framework of OpenRISC1200 processor core is analyzed, and the minimum system is given by cutting the additional units. The minimum system includes integer pipeline unit, register unit and memory. The function of pipeline level, the possible risks in all levels, the conditions for taking risks and the solutions of various adventures are analyzed. This paper introduces the characteristics of Cache technology used in OpenRISC to match the performance difference between main memory and CPU, and analyzes and classifies the characteristics of OpenRISC instruction set. Then, the OpenRISC processor pipeline is simulated by SystemC, and the overall design framework of OpenRISC processor is given, including the simulation of IF module in IF level, the simulation of control module and rf module in ID level, the simulation of operandmuxes module and alu module in EXE level, the simulation of lsu module in MA level and the simulation of wbmux module in WB level. At the same time, the simulation implementation of Cache is given. Finally, combined with SystemC simulation development platform, the necessary initialization work is carried out, and the corresponding test cases are designed for data adventure, pipeline blocking, pipeline synthesis performance and Cache function, and the related code and execution results are given. The theoretical analysis and experimental results show that the simulation of OpenRISC processor core based on simulation language SystemC is feasible, on the basis of which it can be further developed and improved and used to support the development and design of software and hardware system based on OpenRISC.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
本文编号：2502166
[Abstract]:With the increasing function of on-chip system (SoC), the increasing complexity and difficulty of design and the shortening of product marketing cycle, more and more attention has been paid to processor simulation technology. Processor simulation can not only play an important role in the hardware design phase as a reference model for processor function verification, but also play an important role in the software design phase as a system support platform in the software development environment. In order to promote the development of open source OpenRISC processor technology and verify the advantages of processor simulation based on SystemC simulation language, this paper uses SystemC to simulate open source OpenRISC processor, gives the simulation implementation of OpenRISC processor minimum system, and focuses on the design and implementation of OpenRISC pipeline simulation, which can lay a foundation for the further simulation and development of OpenRISC processor based on SystemC. The research work of this paper mainly includes: firstly, the processor simulation technology and SystemC hardware simulation platform are analyzed, and the functional characteristics of instruction set simulation technology and structure simulation technology in processor simulation technology, the design methodology under SystenC hardware simulation platform, the characteristics and functions of simulation kernel and process are introduced in detail. Secondly, the structure framework of OpenRISC1200 processor core is analyzed, and the minimum system is given by cutting the additional units. The minimum system includes integer pipeline unit, register unit and memory. The function of pipeline level, the possible risks in all levels, the conditions for taking risks and the solutions of various adventures are analyzed. This paper introduces the characteristics of Cache technology used in OpenRISC to match the performance difference between main memory and CPU, and analyzes and classifies the characteristics of OpenRISC instruction set. Then, the OpenRISC processor pipeline is simulated by SystemC, and the overall design framework of OpenRISC processor is given, including the simulation of IF module in IF level, the simulation of control module and rf module in ID level, the simulation of operandmuxes module and alu module in EXE level, the simulation of lsu module in MA level and the simulation of wbmux module in WB level. At the same time, the simulation implementation of Cache is given. Finally, combined with SystemC simulation development platform, the necessary initialization work is carried out, and the corresponding test cases are designed for data adventure, pipeline blocking, pipeline synthesis performance and Cache function, and the related code and execution results are given. The theoretical analysis and experimental results show that the simulation of OpenRISC processor core based on simulation language SystemC is feasible, on the basis of which it can be further developed and improved and used to support the development and design of software and hardware system based on OpenRISC.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
【参考文献】
相关期刊论文 前1条
1 杨荣;朱建彬;胡博;朱勇;;基于SystemC的片上系统设计[J];武汉科技学院学报;2008年07期
本文编号：2502166
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