中小规模嵌入式EEPROM IP设计

发布时间：2019-06-21 07:38

【摘要】：进入21世纪以来，便携式消费电子产品的种类越来越多，应用于其中的半导体存储器的新品种也不断涌现。其中非挥发性半导体存储器以其更先进更适应于时代发展的特点成为主流。EEPROM存储器(Electrically ErasableProgrammable Read-Only Memory)就是其中的代表。EEPROM使用单电源供电，使用上十分方便，在嵌入式IC卡市场及通讯系统中被大量应用。论文的主要工作是实现完整的可复用的中小规模EEPROM IP的设计。论文首先研究了EEPROM存储器的工作原理，完成了基准电压源、电荷泵、灵敏放大器、EEPROM Cell单元等关键技术研究，利用Cadence公司的Virtuoso平台对EEPROM的存储阵列、行地址译码、列地址译码、时序电路、数据寄存器、地址寄存器等数字电路模块以及高压产生电路、灵敏放大器电路等模拟电路模块进行了设计、仿真。论文采用先整体规划，再对各个电路分别进行设计的自上而下的方案，结合实验室多年积累的模拟与数字电路设计方面的经验，完成了1K EEPROM IP存储器电路级的设计，并对一部分关键电路模块进行了物理版图的设计。论文设计采用了CSMC（华润上华）0.5μm CMOS工艺，设计的高压产生电路能产生20V的稳定电压，升压时间约220μs，能快速达到工作高压。
[Abstract]:Since the beginning of the 21st century, there are more and more kinds of portable consumer electronics, and new varieties of semiconductor memory are also emerging. Among them, non-volatile semiconductor memory has become the mainstream because it is more advanced and suitable for the development of the times. EEPROM memory (Electrically ErasableProgrammable Read-Only Memory) is the representative of EEPROM. EEPROM uses single power supply and is very convenient to use. EEPROM is widely used in embedded IC card market and communication system. The main work of this paper is to realize the design of reusable small and medium-sized EEPROM IP. Firstly, the working principle of EEPROM memory is studied, and the key technologies such as reference voltage source, charge pump, sensitive amplifier, EEPROM Cell unit and so on are studied. The digital circuit modules such as EEPROM storage array, address decoding, column address decoding, sequential circuit, data register, address register and analog circuit modules such as high voltage generation circuit and sensitive amplifier circuit are designed and simulated by using Virtuoso platform of Cadence Company. In this paper, the top-down scheme of each circuit is designed first, and combined with the experience of analog and digital circuit design accumulated in the laboratory for many years, the circuit level design of 1K EEPROM IP memory is completed, and the physical layout of some key circuit modules is designed. In this paper, CSMC (China Resources Shanghua) 0.5 渭 m CMOS process is used in the design. The high voltage generation circuit can generate a stable voltage of 20V, the boost time is about 220 渭 s, and the working high voltage can be achieved quickly.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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