基于指令插入技术的多核处理器调试系统关键技术研究与实现
发布时间：2019-06-24 13:39
【摘要】：大部分智能电子系统都离不开启动代码、操作系统及应用程序的开发或移植。随着信息技术的飞速发展,软件的设计复杂度和调试难度也越来越大。大型程序的开发离不开良好的处理器硬件调试的支持,特别是启动代码和操作系统的调试更需要处理器本身硬件调试系统的支持。研究人员已经提出了多种调试技术和方法,部分技术已经被广泛应用于软件开发领域,如ICE、调试代理、软件仿真等。但这些调试技术对目前主流的多核多线程处理器的支持还存在一些缺陷,尚不够完善。本文针对自主X3处理器,采用指令插入方法设计实现了支持多线程的单核调试支持部件。在单核调试支持部件的基础上针对多核系统,提出了一种异步互连结构。并在此基础上设计实现了自主多核处理器调试系统。该调试系统能够同时支持处理器Bootloader调试和操作系统调试。本文的创新点和主要工作如下:1)基于复用内核流水线指令提交流水站相应控制信号的方法,提出了一套实现指令地址断点、指令断点、数据断点等匹配与处理的技术方案。由于内核流水线采用分支预测、指令乱序发射等技术,在取指流水站依据指令地址进行断点匹配,必然导致断点的误触发,如何解决这一问题是内核调试支持部件设计的难点之一。本文提出复用流水线指令提交站控制信号并从取指站开始逐站传递指令地址的方案,解决了指令地址断点匹配误触发问题,避免了复杂的流水线行为分析问题,使得本设计方案具有良好的通用性,适用于各种具有指令顺序提交特征的处理器。2)基于指令插入方法设计实现了单个内核的调试支持部件(DSU)。该部件设计方案利用内核本身的流水线并针对调试加以部件改造,以较少的硬件代价实现了对流水线的运行控制、指令插入等操作,使得DSU能够接收来自宿主机的调试命令,执行程序停顿/运行控制、指令断点和数据断点设置、硬件断点和软件断点设置、变量查看与更新等多种复杂的调试操作。3)提出了一种片上异步互连协议——CLB,基于CLB构建了自主多核处理器X3的调试系统。设计实现了针对X3处理器的调试命令接口协议和部件,将来自片外ICE的调试命令转换为DSU接口报文,并传递到目标内核。宿主机调试软件采用了开源的eclipse和GDB调试器,实现了图形化的交叉调试环境。
[Abstract]:Most intelligent electronic systems can not be separated from startup code, operating system and application development or transplantation. With the rapid development of information technology, the design complexity and debugging difficulty of software are becoming more and more difficult. The development of large programs can not be separated from the support of good processor hardware debugging, especially the debugging of startup code and operating system needs the support of processor's own hardware debugging system. Researchers have put forward a variety of debugging techniques and methods, some of which have been widely used in the field of software development, such as ICE, debugging agent, software simulation and so on. However, there are still some defects in the support of these debugging technologies for the current mainstream multi-core multi-thread processor, which is not perfect enough. In this paper, a single core debugging support component supporting multithreading is designed and implemented by using instruction insertion method for autonomous X3 processor. An asynchronous interconnection structure for multi-core systems is proposed on the basis of single-core debugging support components. On this basis, an autonomous multi-core processor debugging system is designed and implemented. The debugging system can support processor Bootloader debugging and operating system debugging at the same time. The innovation and main work of this paper are as follows: 1) based on the method of reusing the kernel pipeline instruction to submit the corresponding control signal of the flow station, a set of technical schemes to realize the matching and processing of instruction address breakpoint, instruction breakpoint, data breakpoint and so on are proposed. Because the kernel pipeline adopts the technology of branch prediction and instruction random sequence transmission, matching the breakpoint according to the instruction address in the fetch flow water station will inevitably lead to the false trigger of the breakpoint. How to solve this problem is one of the difficulties in the design of kernel debugging support components. In this paper, a scheme of reusing pipeline instruction submission station control signal and transmitting instruction address station by station is proposed, which solves the problem of false trigger of instruction address breakpoint matching, avoids the complex problem of pipeline behavior analysis, and makes the design scheme have good generality. It is suitable for all kinds of processors with instruction sequence submission characteristics. 2) the debugging support component (DSU). Of a single kernel is designed and implemented based on instruction insertion method. The component design scheme makes use of the pipeline of the kernel itself and modifies the parts for debugging, and realizes the operation of pipeline operation control and instruction insertion at less hardware cost, so that DSU can receive debugging commands from host computer, execute program pause / operation control, instruction breakpoint and data breakpoint setting, hardware breakpoint and software breakpoint setting. A variety of complex debugging operations, such as variable viewing and updating, are proposed. 3) an on-chip asynchronous interconnection protocol, CLB, is proposed to construct a debugging system of autonomous multi-core processor X3 based on CLB. The debugging command interface protocol and components for X3 processor are designed and implemented. The debugging commands from off-chip ICE are converted into DSU interface messages and passed to the target kernel. The host debugging software adopts open source eclipse and GDB debugger to realize graphical cross-debugging environment.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
，
本文编号：2505100
[Abstract]:Most intelligent electronic systems can not be separated from startup code, operating system and application development or transplantation. With the rapid development of information technology, the design complexity and debugging difficulty of software are becoming more and more difficult. The development of large programs can not be separated from the support of good processor hardware debugging, especially the debugging of startup code and operating system needs the support of processor's own hardware debugging system. Researchers have put forward a variety of debugging techniques and methods, some of which have been widely used in the field of software development, such as ICE, debugging agent, software simulation and so on. However, there are still some defects in the support of these debugging technologies for the current mainstream multi-core multi-thread processor, which is not perfect enough. In this paper, a single core debugging support component supporting multithreading is designed and implemented by using instruction insertion method for autonomous X3 processor. An asynchronous interconnection structure for multi-core systems is proposed on the basis of single-core debugging support components. On this basis, an autonomous multi-core processor debugging system is designed and implemented. The debugging system can support processor Bootloader debugging and operating system debugging at the same time. The innovation and main work of this paper are as follows: 1) based on the method of reusing the kernel pipeline instruction to submit the corresponding control signal of the flow station, a set of technical schemes to realize the matching and processing of instruction address breakpoint, instruction breakpoint, data breakpoint and so on are proposed. Because the kernel pipeline adopts the technology of branch prediction and instruction random sequence transmission, matching the breakpoint according to the instruction address in the fetch flow water station will inevitably lead to the false trigger of the breakpoint. How to solve this problem is one of the difficulties in the design of kernel debugging support components. In this paper, a scheme of reusing pipeline instruction submission station control signal and transmitting instruction address station by station is proposed, which solves the problem of false trigger of instruction address breakpoint matching, avoids the complex problem of pipeline behavior analysis, and makes the design scheme have good generality. It is suitable for all kinds of processors with instruction sequence submission characteristics. 2) the debugging support component (DSU). Of a single kernel is designed and implemented based on instruction insertion method. The component design scheme makes use of the pipeline of the kernel itself and modifies the parts for debugging, and realizes the operation of pipeline operation control and instruction insertion at less hardware cost, so that DSU can receive debugging commands from host computer, execute program pause / operation control, instruction breakpoint and data breakpoint setting, hardware breakpoint and software breakpoint setting. A variety of complex debugging operations, such as variable viewing and updating, are proposed. 3) an on-chip asynchronous interconnection protocol, CLB, is proposed to construct a debugging system of autonomous multi-core processor X3 based on CLB. The debugging command interface protocol and components for X3 processor are designed and implemented. The debugging commands from off-chip ICE are converted into DSU interface messages and passed to the target kernel. The host debugging software adopts open source eclipse and GDB debugger to realize graphical cross-debugging environment.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
，
本文编号：2505100
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