基于现场可编程门阵列的高斯滤波算法优化实现
发布时间：2018-08-27 15:27
【摘要】：针对传统高斯滤波算法硬件设计方法中关键路径较长、逻辑延时较大的问题,提出加数压缩的硬件优化实现方法.在高斯滤波算法优化实现过程中,采用移位操作来实现乘法与除法计算,避免使用乘法器与除法器.并引入保留进位加法器(CSA)、基于多路选择器(MUX)的4-2压缩器、加数压缩的树型结构,对9个加数进行3个层次的压缩.经过优化后,只需1个全加器便可得求和结果.结果表明,经过加数压缩设计可以达到缩短关键路径、减少逻辑延时的目标,使逻辑延时缩小32.48%,同时还极大节省所需加法器宏单元数,为后续图像处理模块提供更大的设计自由度.
[Abstract]:Aiming at the problem of long critical path and long logic delay in the hardware design of traditional Gao Si filtering algorithm, a hardware optimization method of additive compression is proposed. In the process of optimization and implementation of Gao Si filtering algorithm, the shift operation is used to realize multiplication and division calculation, and the multiplier and divider are avoided. The 4-2 compressor based on the multiplexer (MUX) is introduced into the reserved carry adder (CSA), and the tree structure of addition compression is introduced to compress nine additions at three levels. After optimization, only one full adder is needed to obtain the summation result. The results show that after the addition compression design, the key path can be shortened, the logical delay can be reduced by 32.48, and the number of macro cells of the adder can be greatly saved. For the subsequent image processing module to provide a greater degree of freedom.
【作者单位】： 浙江大学电气工程学院;展讯科技(杭州)有限公司;
【基金】：国家“863”高技术研究发展计划资助项目(2012AA041701)
【分类号】：TN713;TP391.41
，
本文编号：2207694
[Abstract]:Aiming at the problem of long critical path and long logic delay in the hardware design of traditional Gao Si filtering algorithm, a hardware optimization method of additive compression is proposed. In the process of optimization and implementation of Gao Si filtering algorithm, the shift operation is used to realize multiplication and division calculation, and the multiplier and divider are avoided. The 4-2 compressor based on the multiplexer (MUX) is introduced into the reserved carry adder (CSA), and the tree structure of addition compression is introduced to compress nine additions at three levels. After optimization, only one full adder is needed to obtain the summation result. The results show that after the addition compression design, the key path can be shortened, the logical delay can be reduced by 32.48, and the number of macro cells of the adder can be greatly saved. For the subsequent image processing module to provide a greater degree of freedom.
【作者单位】： 浙江大学电气工程学院;展讯科技(杭州)有限公司;
【基金】：国家“863”高技术研究发展计划资助项目(2012AA041701)
【分类号】：TN713;TP391.41
，
本文编号：2207694
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