低功耗SoC设计关键技术研究

发布时间：2018-07-01 12:59

本文选题：电子设计自动化 + 片上系统(SoC)　；参考：《宁波大学》2014年博士论文

【摘要】：随着集成电路工艺的发展及便携设备的广泛应用,功耗正在成为芯片设计中继面积和速度以后的重要指标。随着芯片规模的增大和功能的复杂化,集成电路设计技术由基于晶体管、逻辑单元设计步入到基于IP核的SoC设计时代,由此产生的新的层次化设计方法给功耗优化带来了新的挑战。围绕低功耗SoC设计中的关键技术,本文从物理级多电压SoC布图规划、寄存器传输级(Register Transfer Level, RTL)的有限状态机状态分配和电路级的新型CMOS混合电路分别开展研究,提出了有效的低功耗设计优化算法,并采用基准测试电路验证了算法的性能。论文的研究内容主要包含以下几个部分: 1.针对多电压SoC设计中的布图规划,提出了一种有效的算法来进行功耗优化和求解速度的加速。通过松弛电压岛的矩形形状约束,构建非矩形电压岛进一步优化功耗。采用非随机算法完成解空间的搜索加速求解速度,并通过对可能形成一个电压岛的模块建立超图并分割,加快电压岛生成速度。实验结果表明提出的算法在功耗、线长、空白面积和CPU时间上均有优势。 2.针对多电压SoC设计中P/G供电网络的电压降问题,提出了一个基于弹簧模型的电压降感知电源引脚快速分配算法。通过探究影响电压降的关键参数,在布图迭代中考虑电源引脚的分配,进一步实现电压降驱动的电源引脚与布图规划的协同综合。不同于传统的矩阵反转计算得到P/G网络的节点电压降,采用模块到电源引脚的加权距离作为优化参数引导布图产生较低的电压降。然后,采用增量式方法优化电压岛的P/G网络拓扑结构,从而实现P/G网络的布线面积优化。实验结果表明提出的算法可有效改善P/G网络性能,优化了模块和电源引脚的放置。 3.针对多电压SoC布图规划中的电平移位器布局问题,提出了时序约束下的多电压SoC设计流程。在时序和物理约束下同时考虑电压分配、电平移位器布局、电压岛生成等步骤。提出了在网表级插入虚拟电平移位器的方法来保留较多的空白面积,以便于电平移位器布局。与之前的工作不考虑物理信息对电压分配的影响不同,为使时序和物理约束同时得到满足,考虑了物理信息的反馈,通过建立内循环使得电压分配和电平移位器布局交互进行满足直到所有的约束。 4.针对IP核模块中的时序电路,提出了基于拉格朗日松弛技术的峰值电流与开关活动性协同优化算法。通过遗传算法进行解空间的搜索,并在每次迭代中采用次梯度优化算法进行拉格朗日乘子的更新。采用启发式算法确定峰值电流的上界,并返回最优解。通过对IWLS’93和ITC’99的测试电路结果比较,提出的算法较先前的算法可优化峰值电流分别达到45.27%和25.13%；优化开关活动性达6.31%。与确定性方法相比,提出的算法可在较短的CPU时间内得到相同峰值电流。 5.针对新型CMOS混合电路,研究了SoC实现的关键步骤,单元映射算法。通过将映射问题进行拉格朗日松弛,采用包含二维块交叉算子、变异算子和自学习算子的进化算法作为解空间的搜索引擎完成求解。实验结果显示其可增大电路的求解规模,且在面积、时延和CPU时间上均有较大优势；针对高扇出逻辑门难于映射,提出了基于逻辑复制和反相器对插入法进行高扇出的分割完成逻辑变换,实验结果显示变换后的电路进一步改进了性能,降低了映射的复杂度。
[Abstract]:With the development of integrated circuit technology and the wide application of portable equipment , the power consumption is becoming an important index after chip design relay area and speed . With the increase of chip scale and complexity of function , the new hierarchical design method has brought new challenges to power consumption optimization .

1 . Aiming at the layout planning in multi - voltage SoC design , an effective algorithm is put forward to accelerate the power consumption optimization and the solution speed . The non - rectangular voltage island is further optimized by the rectangular shape constraint of the relaxation voltage island . The non - random algorithm is used to complete the search acceleration solution speed of the space . The experimental results show that the proposed algorithm has the advantages of power consumption , line length , blank area and CPU time .

2 . Aiming at the voltage drop problem of P / G power supply network in multi - voltage SoC design , a fast distribution algorithm of voltage drop sensing power supply pin based on spring model is put forward .

3 . In order to solve the problem of level shifter layout in multi - voltage SoC layout planning , a multi - voltage SoC design flow under timing constraints is put forward . At the same time , the steps of voltage distribution , level shifter layout and voltage island generation are considered under the timing and physical constraints .

4 . Aiming at the sequential circuit in IP core module , the optimal algorithm for peak current and switching activity based on Lagrangian relaxation technique is proposed . The algorithm is used to search the solution space . The upper bound of peak current is determined by means of heuristic algorithm , and the optimal solution is returned . The proposed algorithm can optimize the peak current by 45.27 % and 25.13 % by comparing the results of the test circuits of IWLS ' 93 and ITC ' 99 .
The optimized switching activity is 6.31 % . Compared with the deterministic method , the proposed algorithm can obtain the same peak current in the shorter CPU time .

5 . Aiming at the new CMOS hybrid circuits , the key steps and the unit mapping algorithm of SoC implementation are studied . The mapping problem is Lagrangian relaxation , and the evolutionary algorithm including two - dimensional block crossover operator , mutation operator and self - learning operator is used as the search engine to solve the problem . The experimental results show that it can increase the solution size of the circuit and has great advantage in area , time delay and CPU time .
According to the difficult mapping of high - fan - out logic gates , a logic - based replication and inverter - pair insertion method is proposed to perform the high - fan - out logic transformation . The experimental results show that the transformed circuit further improves the performance and reduces the complexity of the mapping .
【学位授予单位】：宁波大学
【学位级别】：博士
【学位授予年份】：2014
【分类号】：TP391.41

【参考文献】