基于FPGA的无线通信信号解调实验平台研制

发布时间：2018-03-11 10:37

本文选题：软件无线电　切入点：FPGA数字信号处理　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：近些年来,随着FPGA(Field Programmable Gate Array)数字信号处理技术及软件无线电的飞速发展,FPGA在通信领域的应用受到了越来越多的关注。针对这一点,本文以FPGA为主要数字信号处理器件,研制了一个无线通信信号解调实验平台。无线通信可以分为两大类:单用户多制式无线通信,如AM(Amplitude Modulation)、FM(Frequency Modulation)等;单制式多用户无线通信,如CDMA(Code Division Multiple Access)、TD-LTE(Time Division Long Term Evolution)等。为了能了解和掌握调制解调的FPGA实现,在第一类中选取了FM、AM(模拟调制)、2ASK、2FSK(数字调制)四种作为解调的实例,并采用归一化瞬时幅度特征,分别在模拟调制和数字调制中来实现调制模式的识别,另外考虑到不同数字调制方式的解调,其FPGA实现已被广泛研究,因此仅研究数字调制解调中的难点,载波同步技术的FPGA实现。在第二类中选取了CDMA扩频系统作为解调实例。同时完成了一个包含射频前端硬件电路和后端数字信号处理的硬件实验平台。射频前端电路,采用超外差接收结构,完成对天线接收到的信号的两次下变频处理及自动增益控制,最终在自动增益控制的输出端可得到一个455k Hz的调频信号;数字信号处理电路,采用A/D采样量化、FPGA上运行算法、D/A将解调的数据输出的方式,来运行各种FPGA调制解调算法。将FM信号的解调算法在后端数字信号处理板上运行,结合射频前端,能听到清楚的调频广播。载波同步采用Costas环来完成,在第二级乘法器中,用一种极其节省资源的近似处理来完成乘法,仿真结果表明,在输入频差在0-100k Hz范围内,均能实现锁定,性能良好。调制模式识别特征的FPGA实现,采用FFT(Fast Fourier Transformation)IP(Intellectual Property)核,结合多级流水线实现累加及控制状态机完成,在Modelsim中的仿真结果表明,不同制式的信号FFT的幂指数部分相差32倍,能有效的完成调制模式识别。在MMSE(Minimum Mean Square Error)多用户检测(Multiuser Detection,MUD)算法的FPGA实现中,本文采用PC机Matlab通过RS232给FPGA发送数据的方式,来完成算法FPGA实现的蒙特卡洛仿真。所得到的误码率,在匹配滤波和MMSE多用户检测算法的理论值之间,考虑到量化和截断所引起的误差,认为该算法在FPGA中实现是正确的。
[Abstract]:In recent years, with the rapid development of digital signal processing technology and software radio technology of FPGA(Field Programmable Gate, the application of FPGA in the field of communication has attracted more and more attention. In this paper, FPGA is used as the main digital signal processing device. A wireless communication signal demodulation experimental platform is developed. Wireless communication can be divided into two categories: single user multi-mode wireless communication, such as AM(Amplitude Modulation / FM Frequency Modulation, single-mode multi-user wireless communication, For example, CDMA(Code Division Multiple access / TD-LTEtime Division Long Term Evolution. In order to understand and master the FPGA implementation of modulation and demodulation, four kinds of FM AM (Analog Modulation 2ASK ~ 2FSKK) are selected as examples of demodulation, and normalized instantaneous amplitude characteristics are adopted. In order to realize modulation pattern recognition in analog modulation and digital modulation respectively, and considering the demodulation of different digital modulation methods, the FPGA implementation has been widely studied, so only the difficulties in digital modulation and demodulation are studied. FPGA implementation of carrier synchronization technology. In the second category, the CDMA spread spectrum system is selected as an example of demodulation. At the same time, a hardware experimental platform including RF front-end hardware circuit and back-end digital signal processing is completed. Using the superheterodyne receiving structure, two downconversion processing and automatic gain control of the signals received by the antenna are completed. Finally, an FM signal of 455kHz can be obtained at the output end of the automatic gain control, the digital signal processing circuit, the digital signal processing circuit, the digital signal processing circuit, the digital signal processing circuit, the digital signal processing circuit, In this paper, we run various FPGA modulation and demodulation algorithms by using the arithmetic of D / A to output the demodulated data on the Ar / D sampling quantized FPGA. The demodulation algorithm of FM signal is run on the back-end digital signal processing board, combined with the RF front-end, and the demodulation algorithm of the FM signal is used in the back-end digital signal processing board. The frequency modulation broadcast can be heard clearly. The carrier synchronization is accomplished by Costas loop. In the second stage multiplier, a resource-saving approximate processing is used to complete the multiplication. The simulation results show that the input frequency difference is in the range of 0-100kHz. The FPGA realization of modulation pattern recognition features is realized by FFT(Fast Fourier Transformation)IP(Intellectual property core, combined with multistage pipeline to realize the accumulation and control state machine. The simulation results in Modelsim show that, The difference of power exponent of different FFT is 32 times, which can effectively realize modulation pattern recognition. In the FPGA implementation of MMSE(Minimum Mean Square error multiuser detection algorithm, this paper uses PC Matlab to send data to FPGA via RS232. The error rate of the algorithm is correct in FPGA, considering the error caused by quantization and truncation between the theoretical values of the matched filter and the MMSE multiuser detection algorithm.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN92;TN911.3

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