阵列雷达回波模拟器的设计

发布时间：2018-04-12 20:18

本文选题：雷达回波模拟器 + 存储器　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着军队电子化水平的快速提升,雷达的作用日益凸显,雷达系统的研制越发地重要和急切。在雷达系统中,信号处理机的作用十分重要,需要经过多次试验来检验信号处理机对回波数据的处理能力。然而,试验通常是在外场进行,一方面,外场试验成本高,容易受环境等外部因素的影响;另一方面,鉴于雷达系统调试是整机调试,如果出现问题,需要对整个雷达系统进行检查进而对问题定位,调试过程比较麻烦。为了解决上述问题,国内外逐渐开始使用雷达回波模拟器对信号处理机进行监控测试。这样不仅节省了人力资源和成本花费,而且方便了调试,很大程度上缩短了雷达系统的研制开发时间。本文讲述的数字阵列雷达回波模拟器采用的是PC机+FPGA的结构,包括数据的产生和数据的存储转换两部分。数据的产生是基于PC机中对应的信号模拟软件实现,包括各种模拟目标信号和各种杂波信号,并将其存储在PC机硬盘中,通过PCI协议传输到模拟器存储设备中;数据的存储转换主要是以FPGA为控制核心,各种接口和存储芯片(NAND FLASH)为辅助设计。一方面,本文讲述的模拟器不但可以使用光纤接收发送数据,同时可以使用网口完成模拟器与局域网中的PC机通信;另一方面,本设计既可以实现将一路阵列信号转化为四十路的阵列信号,也可以为接收的四十路信号加线性调频信号。设计主要有三块电路板,一块是接口板,主要用于控制存储的数据与外界之间的传输;另外两块是存储板,含有大量存储芯片,主要用于存储各种数据。本文的主要内容有:(1)完成模拟器硬件电路的设计,并对设计中相关芯片进行了功能介绍;(2)将PC机产生的一路模拟信号经过CPCI背板由计算机硬盘导入到模拟器的存储设备中,并且经过处理转化为40路模拟信号,然后将信号数据存储起来等待回放;(3)使用光纤接收40路实时信号,并将信号存储到存储设备中,在输出该信号时,每路信号上添加一路线性调频信号作为辅助检测信号;(4)实现PC机和存储设备之间的网口通信。雷达回波模拟器中,各种通信接口起着至关重要的作用,它们是模拟器与外界进行数据传输的纽带,只有通过它们才能实现数据的传输,其中,接口时序的设计是模拟器设计的关键,决定着数据能否正确稳定的传输。
[Abstract]:With the rapid improvement of military electronic level, the role of radar is increasingly prominent, the development of radar system is more and more important and urgent.In radar system, the function of signal processor is very important. It is necessary to test the ability of signal processor to deal with echo data through many experiments.However, the test is usually conducted in the field. On the one hand, the cost of the field test is high, and it is easily affected by external factors such as environment. On the other hand, since the debugging of the radar system is the debugging of the whole machine, if there is a problem,Need to check the entire radar system and then locate the problem, debugging process is more troublesome.In order to solve the above problems, radar echo simulator has been used to monitor and test the signal processor at home and abroad.This not only saves human resource and cost, but also facilitates debugging and shortens the time of radar system research and development to a great extent.The digital array radar echo simulator described in this paper uses the structure of PC FPGA, including data generation and data storage conversion.The data generation is based on the corresponding signal simulation software in PC, including various analog target signals and clutter signals, which are stored in the PC hard disk and transmitted to the simulator storage device through PCI protocol.Data storage conversion is mainly based on FPGA as the control core and various interfaces and memory chips as the aid design.On the one hand, the simulator described in this paper can not only use optical fiber to receive and send data, but also use network interface to complete the communication between simulator and PC in LAN; on the other hand,This design can not only transform one array signal into 40 channel array signal, but also add linear frequency modulation signal to the received 40 channel signal.There are mainly three circuit boards, one is an interface board, mainly used to control the transmission between stored data and the outside world; the other two are memory boards, containing a large number of memory chips, mainly used to store all kinds of data.The main contents of this paper are as follows: 1) complete the hardware circuit design of simulator, and introduce the function of related chip in the design. (2) the analog signal generated by PC is imported from the computer hard disk to the memory device of simulator through the CPCI backplane.After processing, the signal is converted into a 40-channel analog signal, and then the signal data is stored to wait for playback. (3) using optical fiber to receive 40 real-time signals, and storing the signal in the storage device, when the signal is output,A linear frequency modulation (LFM) signal is added to each signal as an auxiliary detection signal to realize the communication between PC and storage device.In radar echo simulator, various communication interfaces play an important role. They are the link between the simulator and the outside world. Only through them can the data be transmitted.The design of interface timing is the key of simulator design, which determines whether the data can be transmitted correctly and stably.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN955

【参考文献】