基于DTMB标准多载波模式的同步系统设计与实现

发布时间：2018-08-31 14:45

【摘要】：时域同步正交频分复用(TDS-OFDM)调制技术具有诸多优点,如抗多径衰落能力强、频谱利用率高等。然而,TDS-OFDM技术也存在其固有的缺点：对接收端同步系统的性能要求较为苛刻。我国的数字电视地面广播DTMB标准的多载波模式中采用TDS-OFDM作为其调制方式。因此,针对DTMB标准的多载波模式的同步系统的设计显得尤为重要,其同步系统的性能直接关系到接收端的质量。本文将基于DTMB标准的多载波模式提出一种同步系统的设计方案,并且对其进行FPGA实现。本文首先着重介绍了现有的DTMB多载波系统的同步技术,并对DTMB多载波系统的发送端和接收端的系统结构、系统帧结构以及同步问题进行了分析。接着,本文提出一种实现DTMB多载波系统同步的流程,设计了其同步系统的运行机制。然后,给出了同步系统的FPGA实现的总体结构,对各个模块进行了实现。最后,将各个模块进行连接,构建完整的同步系统。在系统的同步流程设计方面,将同步系统划分为捕获和跟踪两种状态。所设计的同步流程如下：系统依次进行定时初调整、帧头模式检测及帧头位置粗估计、频偏粗估计及频偏校正、帧头相位捕获、帧头位置细估计、采样细同步、频偏细估计及频偏校正、频偏精估计及频偏校正。借助Matlab软件对该同步流程进行了仿真验证。仿真结果表明,该同步流程能够很好地实现系统同步。在系统的运行机制方面,介绍了捕获和跟踪状态的信号处理流程,并且提出了实现捕获／跟踪状态切换的机制以及突发频偏的处理方法。在状态切换机制上,提出了通过判断定时误差提取器输出的互相关序列的相关峰的尖锐程度以及位置是否发生改变实现状态切换的方法。最后,通过Simulink搭建同步系统,验证了该运行机制的可行性。在同步系统的FPGA实现方面,首先提出了同步系统的FPGA实现的总体架构；接着着重介绍系统各个模块的实现结构,对其中一些模块的实现进行了优化,并对主要模块的实现结果进行了验证；最后将各个模块进行级联,构建完整的同步系统。在FPGA实现过程中,通过采用“乒乓操作”和“串并转换”的方法,提高了系统的处理速度,同时通过采用模块复用、线性逼近法以及数据交织等方法,有效节省了硬件资源。
[Abstract]:Time Domain synchronous orthogonal Frequency Division Multiplexing (TDS-OFDM) has many advantages, such as strong anti-multipath fading ability and high spectral efficiency. However, TDS-OFDM technology also has its inherent shortcomings: the performance of the receiver synchronization system is demanding. In the DTMB standard of digital TV terrestrial broadcasting in China, TDS-OFDM is adopted as the modulation mode in multicarrier mode. Therefore, the design of multi-carrier synchronization system based on DTMB standard is particularly important. The performance of the synchronization system is directly related to the quality of the receiver. In this paper, we propose a design scheme of synchronization system based on multi-carrier mode of DTMB standard, and implement it with FPGA. In this paper, the existing synchronization technology of DTMB multicarrier system is introduced, and the system structure, frame structure and synchronization of DTMB multicarrier system are analyzed. Then, this paper presents a process to realize the synchronization of DTMB multicarrier system, and designs the operation mechanism of the synchronization system. Then, the overall structure of the FPGA implementation of the synchronization system is given, and each module is implemented. Finally, each module is connected to build a complete synchronization system. In the design of synchronization process, the synchronization system is divided into two states: capture and trace. The designed synchronization flow is as follows: the system performs timing initial adjustment, frame head mode detection and frame head position coarse estimation, frequency offset estimation and frequency offset correction, frame head phase capture, frame head position fine estimation, sampling fine synchronization, frame head phase acquisition, frame head position fine estimation, frame head position coarse estimation and frequency offset correction. Frequency offset fine estimation and frequency offset correction, frequency offset precision estimation and frequency offset correction. The synchronization process is verified by Matlab software. Simulation results show that the synchronization process can achieve system synchronization well. In the aspect of system running mechanism, the signal processing flow of acquisition and tracking state is introduced, and the mechanism of acquisition / tracking state switching and the processing method of burst frequency offset are put forward. In the mechanism of state switching, a method is proposed to realize state switching by judging the sharpness of the correlation peak of the cross-correlation sequence outputted by the timing error extractor and whether the position is changed or not. Finally, the synchronization system is built by Simulink, and the feasibility of the operation mechanism is verified. In the aspect of the FPGA implementation of the synchronization system, the overall architecture of the FPGA implementation of the synchronization system is put forward firstly, and then the realization structure of each module of the system is introduced emphatically, and some of the modules are optimized. The implementation results of the main modules are verified. Finally, each module is concatenated to construct a complete synchronization system. In the process of FPGA implementation, the processing speed of the system is improved by using the methods of "ping-pong operation" and "serial-parallel conversion". At the same time, the hardware resources are saved effectively by using the methods of module reuse, linear approximation and data interleaving.
【学位授予单位】：福州大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN949.197

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