去隔行算法的FPGA实现
发布时间：2018-09-14 15:35
【摘要】：随着高清数字电视(HDTV)的推广,人们对视频质量的要求也在逐渐变高。传统的PAL制视频由于分辨率过低,在数字视频上显示让人观感不舒服。同时由隔行扫描带来的画面模糊,运动锯齿现象,让画面显得更加难看,这就会影响在工程实践中实际显示的美感。而且在工程实践中,传统用DSP来实现去隔行的处理,不仅操作繁琐而且也显得太浪费资源。所以运用FPGA来实现视频图像的去隔行便应运而生。本文在开始介绍了FPGA的有关知识,接着便对不同类型的去隔行算法进行了较详细的说明,在对它们进行了比较和分析后,进行了一定改进,给出了一种适合在FPGA上实现的算法,并针对提出的算法,在FPGA上进行了具体的实现。本文的算法是首先运用前后四场的数据进行第一次运动检测,在此同时也进行相应的场内插操作。然后通过场内插数据来进行第二次运动检测,最终将像素点区分为静止点和运动点,并通过选用不同的值,最终获得去隔行的结果。对该算法进行资源实现评估后,将算法划分为具体模块。研究了DDR2 SDRAM芯片的相关操作及其控制器IP核的使用。用VHDL语言对模块进行实现后,下载到FPGA板卡上运行,并在显示器上进行了实时显示。通过观察去隔行的图像,得知该方法能较好的消除模糊、锯齿等不良现象,证明了FPGA方案实现的可靠性,优越性。
[Abstract]:With the promotion of high definition digital TV (HDTV), the requirement of video quality is becoming higher and higher. Traditional PAL video is uncomfortable to display on digital video because of its low resolution. At the same time, the picture blurred by interlacing scan, the phenomenon of motion sawtooth makes the picture look more ugly, which will affect the aesthetic sense of actual display in engineering practice. In engineering practice, the traditional use of DSP to realize the interlacing processing is not only cumbersome operation but also a waste of resources. Therefore, the use of FPGA to achieve video image de-interlacing came into being. This paper introduces the knowledge of FPGA at the beginning, then explains the different kinds of de-interlacing algorithms in detail. After comparing and analyzing them, it improves them, and gives an algorithm that is suitable to be implemented on FPGA. The algorithm is implemented on FPGA. The algorithm of this paper firstly uses the data of four fields to detect the first motion, and carries on the corresponding field interpolation operation at the same time. Then the second motion detection is carried out through the field interpolation data. Finally, the pixels are divided into static points and moving points. Finally, the results of de-interlacing are obtained by selecting different values. After evaluating the resource of the algorithm, the algorithm is divided into specific modules. The related operation of DDR2 SDRAM chip and the use of IP core are studied. After the module is implemented in VHDL language, it is downloaded to the FPGA board to run and displayed in real time on the monitor. By observing the interlaced images, we can see that this method can eliminate the bad phenomena such as blur and sawtooth, and prove the reliability and superiority of the FPGA scheme.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN941
本文编号：2243127
[Abstract]:With the promotion of high definition digital TV (HDTV), the requirement of video quality is becoming higher and higher. Traditional PAL video is uncomfortable to display on digital video because of its low resolution. At the same time, the picture blurred by interlacing scan, the phenomenon of motion sawtooth makes the picture look more ugly, which will affect the aesthetic sense of actual display in engineering practice. In engineering practice, the traditional use of DSP to realize the interlacing processing is not only cumbersome operation but also a waste of resources. Therefore, the use of FPGA to achieve video image de-interlacing came into being. This paper introduces the knowledge of FPGA at the beginning, then explains the different kinds of de-interlacing algorithms in detail. After comparing and analyzing them, it improves them, and gives an algorithm that is suitable to be implemented on FPGA. The algorithm is implemented on FPGA. The algorithm of this paper firstly uses the data of four fields to detect the first motion, and carries on the corresponding field interpolation operation at the same time. Then the second motion detection is carried out through the field interpolation data. Finally, the pixels are divided into static points and moving points. Finally, the results of de-interlacing are obtained by selecting different values. After evaluating the resource of the algorithm, the algorithm is divided into specific modules. The related operation of DDR2 SDRAM chip and the use of IP core are studied. After the module is implemented in VHDL language, it is downloaded to the FPGA board to run and displayed in real time on the monitor. By observing the interlaced images, we can see that this method can eliminate the bad phenomena such as blur and sawtooth, and prove the reliability and superiority of the FPGA scheme.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN941
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1 周津;高清视频去隔行处理系统的关键技术研究[D];天津大学;2008年
中国硕士学位论文全文数据库 前1条
1 李旭;基于运动补偿的去隔行系统的研究与FPGA设计[D];大连理工大学;2005年
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