中子数字成像FPGA抗辐照技术研究
发布时间：2018-07-21 21:55
【摘要】：中子数字成像试验中,现场可编程门阵列(FPGA)是重要的成像逻辑控制器件。然而,中子辐照易引起FPGA的单粒子效应,对中子成像引入本底噪声,因此必须采取措施,减少中子辐照对FPGA成像的影响。结合图像周期性的特点,采用三判二的技术方法替代三模冗余,裁决成像关键信号;采用硬件实现的中值滤波算法,平滑由于RAM区单粒子翻转等原因呈现在图像上的噪点。仿真结果表明,本文采用的两种技术方法不但降低资金成本,提高FPGA资源冗余度,而且在取得良好的抗辐照滤波效果的同时,保留图像细节。时序仿真和硬件平台验证了设计的正确性。
[Abstract]:In the neutron digital imaging test, the field programmable gate array (FPGA) is an important imaging logic control device. However, the neutron irradiation is easy to cause the single particle effect of FPGA, and the neutron imaging is introduced to the background noise. Therefore, measures must be taken to reduce the effect of neutron irradiation on the imaging of FPGA. Combined with the characteristics of the periodicity of the image, a three judgment of two is adopted. The method replaces the three mode redundancy to adjudication the key signal of imaging, and uses the median filtering algorithm implemented by hardware to smooth the noise on the image because of the single particle flip of the RAM region. The simulation results show that the two methods used in this paper not only reduce the cost of capital, raise the redundancy of FPGA resources, but also obtain good radiation resistance. While preserving the image details, timing simulation and hardware platform verify the correctness of the design.
【作者单位】： 东北师范大学物理学院;中国科学院长春光学精密机械与物理研究所;
【基金】：国家自然科学基金项目(11305034) 吉林省科技发展计划项目(20150520084JH) 吉林省教育厅十二五科技项目(2014B042)
【分类号】：O571.53
本文编号：2136976
[Abstract]:In the neutron digital imaging test, the field programmable gate array (FPGA) is an important imaging logic control device. However, the neutron irradiation is easy to cause the single particle effect of FPGA, and the neutron imaging is introduced to the background noise. Therefore, measures must be taken to reduce the effect of neutron irradiation on the imaging of FPGA. Combined with the characteristics of the periodicity of the image, a three judgment of two is adopted. The method replaces the three mode redundancy to adjudication the key signal of imaging, and uses the median filtering algorithm implemented by hardware to smooth the noise on the image because of the single particle flip of the RAM region. The simulation results show that the two methods used in this paper not only reduce the cost of capital, raise the redundancy of FPGA resources, but also obtain good radiation resistance. While preserving the image details, timing simulation and hardware platform verify the correctness of the design.
【作者单位】： 东北师范大学物理学院;中国科学院长春光学精密机械与物理研究所;
【基金】：国家自然科学基金项目(11305034) 吉林省科技发展计划项目(20150520084JH) 吉林省教育厅十二五科技项目(2014B042)
【分类号】：O571.53
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