基于TMS320C6678的H.264图像压缩编码技术研究

发布时间：2018-06-13 22:24

本文选题：x264 + 多核DSP　；参考：《中国科学院研究生院(光电技术研究所)》2016年硕士论文

【摘要】：图像是人们获取信息最直观、最重要的来源。随着工业控制、航天等领域对图像质量要求的逐步提升以及图像传感器技术和处理器的发展,高帧频、高分辨率成像技术有了快速的发展,且应用也越来越广泛。高帧频、高分辨率成像技术会产生大量的图像数据,为了在有限的带宽内实时获取图像信息,需对图像实时压缩,因此图像的实时压缩成为研究的重点。对于这个问题,本文通过对H.264图像编码标准和多核DSP的研究,以x264开源代码为基础,在TMS320C6678上展开H.264并行编码以及相应优化技术的研究。首先,论文阐述了图像压缩标准和图像压缩实现技术现状,从多种压缩标准和实现技术中选取x264开源代码加多核DSP模式实现H.264标准的图像压缩。其次,介绍了TMS320C6678的硬件结构、软件编程结构、核间通信模型、并行调度方案以及多核加载模式,为后面x264代码的并行与优化以及压缩平台上电自起奠定了基础。然后,对H.264图像压缩标准以及并行算法相关知识展开说明。从图片组、帧、片以及宏块四个层次对H.264的并行压缩编码技术进行了分析,通过对比选取Slice级为并行编码模型。最后结合x264开源代码特点在TMS320C6678平台上实现了H.264标准的图像编码,主要做的工作包括:编写上位机软件,用于向压缩平台发送图像数据与接收压缩数据;修改x264源码使其符合CCS编译规则,调整内存布局,在DSP上初步实现H.264图像压缩编码;采用动态Slice划分和静态Slice划分算法将一帧图像划分为若干片,利用OpenMP并行调度方案,将划分后的Slice分配到C6678的core0-core6实现编码器的Slice级并行;采用项目级优化、内联函数嵌入、软件流水等方式对编码器进行优化,提高编码速率。通过对编码器并行化与优化处理前后编码速率的比较,基于TMS320C6678平台的编码速率由3.30帧/秒提升到159.98帧/秒。由此可以看出对编码器的片级并行处理与后续优化有效的提升了编码速率。
[Abstract]:Image is the most direct and important source of information. With the gradual improvement of image quality requirements in industrial control, aerospace and other fields, as well as the development of image sensor technology and processor, high frame rate, high resolution imaging technology has been rapidly developed, and its application is becoming more and more extensive. High frame rate, high resolution imaging technology will produce a lot of image data. In order to obtain image information in a limited bandwidth, real-time image compression is needed, so real-time image compression becomes the focus of research. To solve this problem, based on the research of H.264 image coding standard and multi-core DSP, and based on x264 open source code, this paper develops the research of H.264 parallel coding and corresponding optimization technology on TMS320C6678. Firstly, this paper describes the current situation of image compression standard and image compression implementation technology, and selects x264 open source code and multi-core DSP mode to realize H.264 image compression from various compression standards and implementation technologies. Secondly, the hardware structure, software programming structure, inter-core communication model, parallel scheduling scheme and multi-core loading mode of TMS320C6678 are introduced. Then, the H.264 image compression standard and related knowledge of parallel algorithms are explained. The parallel compression coding technology of H. 264 is analyzed from four levels: picture group frame slice and macroblock. Slice level is chosen as the parallel coding model by comparison. Finally, the image coding of H.264 standard is implemented on TMS320C6678 platform with the characteristics of x264 open source code. The main work includes: writing the upper computer software to send image data and receive compressed data to the compression platform; Modifying x264 source code to conform to CCS compiling rules, adjusting memory layout, realizing H.264 image compression coding on DSP, using dynamic slice partition and static slice partition algorithm to divide a frame image into several pieces, using OpenMP parallel scheduling scheme, The partition slice is allocated to the core0-core6 of C6678 to realize the slice level parallelism of the encoder, and the encoder is optimized by item level optimization, inline function embedding, software pipelining and so on, so as to improve the coding speed. The encoding rate based on TMS320C6678 platform is increased from 3.30 frame / s to 159.98 frame / s by comparing the coding rate before and after the parallelization and optimization of the encoder. It can be seen that the chip level parallel processing and subsequent optimization of the encoder can effectively improve the coding rate.
【学位授予单位】：中国科学院研究生院(光电技术研究所)
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN919.81

【相似文献】