面向5G的多元LDPC码研究及实现

发布时间：2018-06-17 23:00

本文选题：多元LDPC码 + 异构计算　；参考：《东南大学》2017年硕士论文

【摘要】：1963年Gallager提出了 LDPC码概念,同时也引入了基于模运算的多元LDPC码。1998年,Davey和MacKay将多元LDPC码扩展到高阶的有限域GF(q)上。多元LDPC码在中短码长区域有着卓越的性能,然而过高的译码复杂度限制了它的实际应用。本文将主要对多元LDPC码的构造方案,编、解码器的实现方案以及多元LDPC码的应用进行研究。论文将介绍多元LDPC码基于消息传递的迭代译码算法,包括多元乘积求和算法(QSPA),拓展最小和算法(EMS)等,以及基于格型图的拓展最小和算法(T-EMS)。论文详细阐述这几类算法的具体译码步骤,同时结合具体的多元LDPC码码字进行仿真,分析研究参数优化的结果并综合比较不同算法的译码性能与复杂度。论文给出一种多元准循环原型图LDPC(NB-QC-PLDPC)码构造方案。首先,论文详细描述外附信息转移图(EXIT)的具体步骤并分析门限值与GF(q)阶数的关系,为构造方案提供理论依据。接着,论文给出构造方案的每个步骤,包括原型图结构的优化、移位参数的优化放置和非零元组的选择。论文通过构造具体码字对不同编码方案进行分析和比较。在极短码长kk = 96,R=0.5情形下,NB-QC-PLDPC码的性能均优于卷积码、Turbo码、WiMAX和CCSDS结构的二元LDPC码,获得了与Polar相近的性能,相较于Turbo在BLER = 10-3处约有1dB的性能增益。同时,也考虑多种码长和高码率场景,本文构造的NB-QC-PLDPC码均表现出了优异的性能。论文实现基于FPGA的异构计算平台,提出并实现具有线性编码复杂度码字的多元LDPC码编码器和全并行结构的解码器。首先,论文给出通过PCIe接口实现FPGA与CPU协同计算的实现结果,系统整体速率最高达190Mbps,可满足现有通信系统速率要求。接着,论文给出多元LDPC码编码器的设计与实现,详细阐述编码器中的关键模块的原理及实现方式,包括GF(q)乘法运算和编码过程两方面。最后,论文给出全并行的多元LDPC码解码器的设计及实现,详细描绘解码器中的若干关键模块及相应设计框图,分别为变量节点、交织节点和校验节点处理单元。论文探讨在双向中继系统的物理层网络编码方案中采用多元LDPC码译码算法,通过大量仿真验证采用多元LDPC码译码算法的优势。首先,将中继端的码字组合看作一种特殊的多元LDPC码给出了广义的联合信道译码及网络编码算法。接着,针对中继端相位异步的问题,论文提出一种符号预旋转方案。仿真结果表明,该方案充分利用多元LDPC码译码算法的纠错能力,大幅提高了最差信道相位情况下整个双向中继系统的通过率。
[Abstract]:In 1963 Gallager proposed the concept of LDPC codes and introduced multivariate LDPC codes based on modular operations. In 1998 Davey and MacKay extended multivariate LDPC codes to higher-order finite field GFPQ codes. Multivariate LDPC codes have excellent performance in medium and short code length areas, but their practical applications are limited by their high decoding complexity. In this paper, the construction scheme, encoder and decoder scheme of multivariate LDPC codes and the application of multivariate LDPC codes are studied. In this paper, the iterative decoding algorithm based on message passing for multivariate LDPC codes is introduced, including multiple product summation algorithm (QSPAA), extended minimum sum algorithm (EMSS), and extended minimum sum algorithm (T-EMSA) based on trellis graph. In this paper, the detailed decoding steps of these algorithms are described in detail. At the same time, the simulation is carried out with the specific LDPC codewords, and the results of parameter optimization are analyzed and the decoding performance and complexity of different algorithms are compared synthetically. In this paper, a scheme of constructing LDPC-NB-QC-PLDPC code based on multivariate quasi-cyclic prototype graph is presented. Firstly, the paper describes the concrete steps of exiting information transfer graph in detail and analyzes the relationship between threshold value and GFQ order, which provides a theoretical basis for the construction scheme. Then, each step of the construction scheme is given, including the optimization of the prototype graph structure, the optimal placement of shift parameters and the selection of non-zero tuples. This paper analyzes and compares different coding schemes by constructing concrete codewords. The performance of NB-QC-PLDPC code is better than that of convolutional code Turbo code WiMAX and CCSDS structure, and the performance is similar to Polar. Compared with Turbo code at BLER = 10-3, the performance of NB-QC-PLDPC code is similar to that of Polar code. The performance gain of NB-QC-PLDPC code is about 1 dB compared with that of Turbo code at BLER = 10 ~ (-3). At the same time, the NB-QC-PLDPC codes constructed in this paper have excellent performance considering many kinds of code length and high bit rate scenes. In this paper, a heterogeneous computing platform based on FPGA is implemented, and a multivariate LDPC encoder with linear coding complexity and a full parallel decoder are proposed and implemented. First of all, the paper gives the implementation results of FPGA and CPU collaborative computing through PCIe interface. The overall speed of the system is up to 190Mbpss, which can meet the requirements of the existing communication system. Then, the paper gives the design and implementation of the multivariate LDPC encoder. The principle and implementation of the key modules in the encoder are described in detail, including the multiplication operation and the coding process. Finally, the design and implementation of a multivariate LDPC decoder with full parallelism are presented. The key modules and corresponding design block diagrams of the decoder are described in detail, including variable node, interleaved node and check node processing unit. In this paper, the decoding algorithm of multiple LDPC codes in the physical layer network coding scheme of bidirectional relay system is discussed, and the advantages of the decoding algorithm of multiple LDPC codes are verified by a large number of simulations. Firstly, the code-word combination at the relay end is regarded as a special multivariate LDPC code. The generalized joint channel decoding and network coding algorithms are presented. Then, aiming at the asynchronous phase of relay terminal, a symbol prerotation scheme is proposed in this paper. The simulation results show that the scheme makes full use of the error correction ability of the multivariate LDPC decoding algorithm and greatly improves the pass rate of the whole bidirectional relay system under the worst channel phase.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22

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