嵌入式领域ECC专用指令处理器的研究

发布时间：2018-06-24 19:23

本文选题：椭圆曲线密码 + 专用指令处理器　；参考：《计算机学报》2017年05期

【摘要】：与其他公钥密码算法相比,椭圆曲线密码算法(Elliptic Curve Cryptography,ECC)具有抗攻击能力强、计算量小以及处理速度快等优点,已成为下一代公钥密码体制的标准.随着ECC在嵌入式领域的应用日益广泛,如何提高其执行效率成为目前研究的热点问题.文中提出了一套通用的专用指令处理器(Application Specific Instruction Processor,ASIP)的设计验证方案,并将该方案应用于ECC,从而大幅提升其在硬件资源受限的嵌入式环境中的执行效率.首先借鉴并实现了OpenSSL公开的ECC软件优化方案,并结合处理器平台的特点对大整数乘法运算和多项式平方运算进行了进一步优化.其次对优化后的算法进行基本指令块(Basic Instruction Block,BIB)的划分并转化为数据流图(Data Flow Graph,DFG),在DFG图中依照专用指令设计规则引入近似最优解方法查找可优化指令块.对该类指令块设计相应的专用指令,以实现处理器原有基础指令集架构的扩展.再次基于电子系统级(Electronic System Level,ESL)设计方法依次设计并仿真验证ECC_ASIP的系统级模型和Verilog寄存器传输级(Register Transfer Level,RTL)模型.最后将验证通过的RTL级处理器模型进行综合、布局布线,转换成相对应的门级电路并统计模型使用的硬件资源信息,烧写到FPGA(Field-Programmable Gate Array)平台完成ECC_ASIP的移植操作和性能验证.与ARM11处理器平台下算法实现的性能表现进行对比,实验结果显示,ECC_ASIP牺牲了9.23x%的硬件扩展资源,将算法实现的运算速度提高了2.74x倍,指令代码存储空间减少了59.36x%.
[Abstract]:Compared with other public key cryptography algorithms, Elliptic Curve Cryptograph ECC (ECC) has become the standard of the next generation public key cryptosystem because of its strong anti-attack ability, small computation and fast processing speed. With the increasing application of ECC in embedded field, how to improve its execution efficiency has become a hot issue. In this paper, a design and verification scheme of Application specific instruction processor (ASIP) is proposed, and the scheme is applied to Ecc, which greatly improves its execution efficiency in embedded environment with limited hardware resources. The ECC software optimization scheme published by OpenSSL is first used for reference and implemented, and the large integer multiplication and polynomial square operation are further optimized according to the characteristics of the processor platform. Secondly, the optimized algorithm is divided into basic instruction block (BIB) and transformed into data flow graph (DFG). According to the special instruction design rules, the approximate optimal solution method is introduced to find the optimized instruction block in the DFG diagram. The corresponding special instructions are designed to implement the extension of the original basic instruction set architecture of the processor. Based on the design method of Electronic system level ESL (Electronic system level ESL), the system level model and Register transfer level RTL model of ECCS ASIP are designed and simulated. Finally, the verified RTL-level processor model is synthesized, wired, converted into the corresponding gate circuit, and the hardware resource information used by the model is counted, and written to the FPGA (Field-Programmable Gate Array) platform to complete the porting operation and performance verification of ECCSIP. Compared with the performance of the algorithm implemented on ARM11 processor platform, the experimental results show that ECCS ASIP sacrificed 9.23x% of hardware extension resources, increased the speed of the algorithm by 2.74x, and reduced the storage space of instruction code by 59.36x.
【作者单位】：青岛大学计算机科学技术学院;青岛大学系统科学博士后流动站自动化与电气工程学院;山东大学山东省软件工程重点实验室;中国科学院信息工程研究所信息安全国家重点实验室;
【基金】：国家自然科学基金(61402245,61572267,61272425,61170106,11472144) 国家科技支撑计划子课题(2014BAG03B05) “十二五”国家密码发展基金(MMJJ201301011) 中国博士后科学基金第八批特别资助(2015T80696);中国博士后科学基金面上项目(2014M551870) 山东省自然科学基金(ZR2014FQ010) 青岛市博士后应用研究项目山东省软件工程重点实验室开放课题(2013SE01)资助~~
【分类号】：TN918.4

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