基于FPGA的AES算法硬件实现优化及其系统设计

发布时间：2018-07-27 17:06

【摘要】：为了保证用户的重要信息或数据在网络与通信中不被未经授权的第三方盗取,用户需要将数据加密之后进行通信。通常,最常用的数据加密方式是软件加密,即在通用微处理器上编程实现,但其加密速度普遍不高,算法实现的效率较低,安全性和可靠性有限,很多时候不能满足用户的需求。因此,需要更加快速,更加安全可靠的加密实现方式来满足人们在一些场合下的数据保密要求。基于FPGA的加密算法实现具有安全性高,加密速度快,开发周期短,开发成本较低,可重配,可靠性高以及移植性好等优点。所以,这种数据加密方式的获得了越来越多的关注。本论文在研究AES(Advanced Encryption Standard)算法基本原理及其相关数学理论知识的基础上,从四个方面对AES算法的FPGA硬件实现进行优化:首先,在总体设计上采用混合流水线结构:轮迭代间采用完全展开流水线结构,轮内采用流水线结构;其次,字节替代与行移位组合实现,减少行移位资源占用,字节替代,列混淆,密钥拓展模块使用查找表进行优化,降低运算复杂度和资源占用,通过找出关键路径并进行优化,再次提升加密速度;然后,加密过程与解密过程两者共享密钥拓扩展模块及查找替换表模块,减少了可编程逻辑资源的消耗;最后,通过FPGA内嵌的RAM(BRAM)预存查找表,从而进一步减少FPGA芯片面积的消耗。对优化后的AES算法进行综合、时序约束、布局布线,同时获得资源消耗与工作频率等参数,并与同类研究进行对比。结果证明,本设计实现了较快的加/解密速度,且资源消耗较低,在加/解密效率上有很大优势。在AES算法硬件实现优化基础上,利用自定制IP核技术将优化后的AES算法封装成IP软核,以便于在任何FPGA芯片上复用。最后,在自定制AES IP核的基础上,完成整个AES加/解密系统的设计。在专业仿真工具Modelsim上仿真验证AES加/解密系统,然后使用Quartus II集成开发环境进行综合,布局布线,时序约束。最后下载到DE2开发板上进行验证,实验结果表明AES加/解密系统可以正常且稳定的运行在200M的时钟频率下,加密速度可以达到6.4Gbit/s,可以满足绝大多数的网络或通信中的数据加密。整个系统结构简单,可自由配置功能模块,安全性高,移植性好,便于实时维护,可以广泛的用于多种信息安全领域。
[Abstract]:In order to ensure that the important information or data of users are not stolen by unauthorized third parties in the network and communication, users need to encrypt the data and communicate. Usually, the most commonly used data encryption method is software encryption, that is, it is programmed on a general-purpose microprocessor, but its encryption speed is generally not high, the efficiency of the algorithm is low, and the security and reliability are limited. In many cases, it can not meet the needs of the user. Therefore, a faster, more secure and reliable encryption method is needed to meet the requirements of data security in some situations. The implementation of encryption algorithm based on FPGA has the advantages of high security, fast encryption speed, short development period, low development cost, rematch, high reliability and good portability. Therefore, this kind of data encryption method has gained more and more attention. On the basis of studying the basic principle of AES (Advanced Encryption Standard) algorithm and its related mathematical theory knowledge, this paper optimizes the FPGA hardware implementation of AES algorithm from four aspects: first of all, In the overall design, the hybrid pipeline structure is adopted: the fully expanded pipeline structure is adopted between wheel iterations, and the pipeline structure is adopted in the wheel; secondly, the combination of byte substitution and row shift is realized to reduce the resource occupation of row shift, byte substitution, column confusion, etc. Key expansion module uses lookup table to optimize, reduce computational complexity and resource occupation, by finding critical path and optimization, improve encryption speed again; then, The encryption process and decryption process share the key extension module and the lookup replacement table module to reduce the consumption of programmable logic resources. Finally, the area consumption of FPGA chip is further reduced by the RAM (BRAM) pre-stored lookup table embedded in FPGA. The optimized AES algorithm is synthesized, timing constraint, layout and routing, and the parameters such as resource consumption and working frequency are obtained, and compared with the similar research. The results show that the design achieves faster encryption / decryption speed and lower resource consumption, and has a great advantage in encryption / decryption efficiency. On the basis of hardware optimization of AES algorithm, the optimized AES algorithm is encapsulated into IP soft core by using custom IP kernel, which is easy to reuse on any FPGA chip. Finally, on the basis of custom AES IP core, the whole AES encryption / decryption system is designed. The AES encryption / decryption system is simulated and verified on the professional simulation tool Modelsim, and then the Quartus II integrated development environment is used for synthesis, layout, routing and timing constraints. The experimental results show that the AES encryption / decryption system can run normally and stably at 200m clock frequency, and the encryption speed can reach 6.4 Gbit / s, which can satisfy most of the data encryption in network or communication. The whole system has the advantages of simple structure, free configuration of function modules, high security, good portability, convenient real-time maintenance, and can be widely used in many kinds of information security fields.
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN918.4

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