极化码性能研究及CA-SCL译码器的FPGA实现
发布时间：2018-08-24 15:39
【摘要】：随着社会的进步,移动通信技术已进入5G新时代,极化码(Polar Code)作为5G的热门备选编码方案正受到广泛的关注和研究。近几年来,虽然有成熟的Turbo码和LDPC码这些高效实用的信道编码,但它们的误码性能与香农限存在一些差距,而极化码是唯一在理论上证明能达到香农极限的编码。目前,极化码作为控制信道的编码方案,已被写入5G标准中。极化码由Arikan在2008年发现并提出,其产生基础是基于离散二进制无记忆信道(B-DMC)的极化现象,其编码和译码均具有高效且易于实现的结构,因而具有很大的应用潜力。本文的主要研究了有限码长下极化码的码字构造方法和译码算法,以及设计基于CA-SCL算法的译码器的硬件结构和FPGA实现。具体工作如下:首先介绍了现有的Turbo码和LDPC码这两种可迭代的编码,详细介绍了它们的编译码结构和算法,仿真模拟了译码性能,指出Turbo码会出现错误平台现象,非规则LDPC码的编码复杂度高,最后介绍了极化码,并从码字构造、编码和译码三个方面做比较,证明了极化码的优越性。其次详细介绍了极化码的产生原理,研究了信道分解和信道合并过程中发生信道极化时,BEC等信道模型的参数变化规律,仿真分析了极化定理的实质,并引出极化编码理论。具体分析了生成矩阵的产生和编码流程,并基于编码原理研究了码字构造方法,提出了针对不同信道环境的信息位选择方法,对每种方法进行性能分析,结果表明高斯近似方法更具有实用价值。最后研究了Plotkin结构的RM码与极化码的异同。然后研究了极化码的译码算法。在基础SC算法上提出了运算改进型的LLR近似计算和性能改进型的SCL译码方法。SCL译码算法在SC的基础上增加了多条路径的选择,使得算法性能接近于ML译码的性能,CA-SCL在SCL方法的基础上增加了冗余校验CRC码,迭代译码时对输出的序列进行CRC过滤,一旦某序列校验和为零则直接作为译码结果输出并停止迭代。CRC码校验进一步提高SCL算法的纠错能力,将此方法作为最后硬件实现的译码方法。最后对CA-SCL译码器进行FPGA硬件结构的设计。针对CA-SCL译码的各个环节,分别设计相关的子功能模块,在QuartusII软件上完成了verilog程序输入,在Modelsim中完成功能仿真和调试,仿真成功后,在译码器顶层模块得到译码的输出结果。所设计的循环冗余SCL译码器在工作频率300Mhz时达到6.5Mbps的吞吐率。
[Abstract]:With the development of society, mobile communication technology has entered a new era of 5G. Polarization code (Polar Code), as a popular alternative coding scheme of 5G, is receiving extensive attention and research. In recent years, although there are mature Turbo codes and LDPC codes as efficient and practical channel codes, there are some differences between their error performance and Shannon's limit, and polarization codes are the only codes that can reach Shannon's limit in theory. At present, polarization code, as a coding scheme of control channel, has been written into 5 G standard. Polarization code was discovered and proposed by Arikan in 2008. It is based on polarization phenomenon of discrete binary memoryless channel (B-DMC). Its coding and decoding are both efficient and easy to implement, so they have great application potential. This paper mainly studies the codeword construction and decoding algorithm of the polarization code with finite code length, and designs the hardware structure and FPGA implementation of the decoder based on CA-SCL algorithm. The main work is as follows: firstly, two kinds of iterative codes, Turbo code and LDPC code, are introduced, their encoding and decoding structures and algorithms are introduced in detail, the decoding performance is simulated, and the error platform phenomenon of Turbo code is pointed out. The coding complexity of irregular LDPC codes is high. Finally, the polarization codes are introduced, and the advantages of polarization codes are proved by comparing them from three aspects: code construction, coding and decoding. Secondly, the generation principle of polarization codes is introduced in detail, and the variation law of the parameters of channel models such as BEC when channel polarization occurs during channel decomposition and channel merging is studied. The essence of polarization theorem is simulated and the polarization coding theory is introduced. The generation and coding process of the generation matrix are analyzed in detail. Based on the coding principle, the codeword construction method is studied, and the information bit selection method for different channel environments is proposed, and the performance of each method is analyzed. The results show that the Gao Si approximation method is more practical. Finally, the similarities and differences between RM codes and polarimetric codes with Plotkin structure are studied. Then the decoding algorithm of polarization code is studied. Based on the basic SC algorithm, an improved LLR approximate algorithm and a performance modified SCL decoding algorithm are proposed. Based on the SC algorithm, the multiple paths are added to the algorithm. Making the performance of the algorithm close to that of ML decoding, CA-SCL adds redundancy check CRC code on the basis of SCL method, and filters the output sequence by CRC during iterative decoding. Once a sequence check sum is zero, it is output directly as decoding result and the iterative. CRC code check is stopped to further improve the error-correcting ability of SCL algorithm. This method is used as the final decoding method implemented by hardware. Finally, the FPGA hardware structure of CA-SCL decoder is designed. For each link of CA-SCL decoding, the related sub-function modules are designed, the verilog program input is completed on the QuartusII software, and the function simulation and debugging are completed in the Modelsim. After the simulation is successful, the decoding output results are obtained in the decoder top-level module. The designed cyclic redundant SCL decoder achieves the 6.5Mbps throughput at the operating frequency 300Mhz.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22
本文编号：2201269
[Abstract]:With the development of society, mobile communication technology has entered a new era of 5G. Polarization code (Polar Code), as a popular alternative coding scheme of 5G, is receiving extensive attention and research. In recent years, although there are mature Turbo codes and LDPC codes as efficient and practical channel codes, there are some differences between their error performance and Shannon's limit, and polarization codes are the only codes that can reach Shannon's limit in theory. At present, polarization code, as a coding scheme of control channel, has been written into 5 G standard. Polarization code was discovered and proposed by Arikan in 2008. It is based on polarization phenomenon of discrete binary memoryless channel (B-DMC). Its coding and decoding are both efficient and easy to implement, so they have great application potential. This paper mainly studies the codeword construction and decoding algorithm of the polarization code with finite code length, and designs the hardware structure and FPGA implementation of the decoder based on CA-SCL algorithm. The main work is as follows: firstly, two kinds of iterative codes, Turbo code and LDPC code, are introduced, their encoding and decoding structures and algorithms are introduced in detail, the decoding performance is simulated, and the error platform phenomenon of Turbo code is pointed out. The coding complexity of irregular LDPC codes is high. Finally, the polarization codes are introduced, and the advantages of polarization codes are proved by comparing them from three aspects: code construction, coding and decoding. Secondly, the generation principle of polarization codes is introduced in detail, and the variation law of the parameters of channel models such as BEC when channel polarization occurs during channel decomposition and channel merging is studied. The essence of polarization theorem is simulated and the polarization coding theory is introduced. The generation and coding process of the generation matrix are analyzed in detail. Based on the coding principle, the codeword construction method is studied, and the information bit selection method for different channel environments is proposed, and the performance of each method is analyzed. The results show that the Gao Si approximation method is more practical. Finally, the similarities and differences between RM codes and polarimetric codes with Plotkin structure are studied. Then the decoding algorithm of polarization code is studied. Based on the basic SC algorithm, an improved LLR approximate algorithm and a performance modified SCL decoding algorithm are proposed. Based on the SC algorithm, the multiple paths are added to the algorithm. Making the performance of the algorithm close to that of ML decoding, CA-SCL adds redundancy check CRC code on the basis of SCL method, and filters the output sequence by CRC during iterative decoding. Once a sequence check sum is zero, it is output directly as decoding result and the iterative. CRC code check is stopped to further improve the error-correcting ability of SCL algorithm. This method is used as the final decoding method implemented by hardware. Finally, the FPGA hardware structure of CA-SCL decoder is designed. For each link of CA-SCL decoding, the related sub-function modules are designed, the verilog program input is completed on the QuartusII software, and the function simulation and debugging are completed in the Modelsim. After the simulation is successful, the decoding output results are obtained in the decoder top-level module. The designed cyclic redundant SCL decoder achieves the 6.5Mbps throughput at the operating frequency 300Mhz.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22
【参考文献】
相关硕士学位论文 前2条
1 郑芝芳;基于Polar码的OFDM系统图像传输的应用研究[D];南京邮电大学;2012年
2 杨秀云;非理想协作通信系统及其联合迭代译码性能的研究[D];南京航空航天大学;2010年
，本文编号：2201269
本文链接：https://www.wllwen.com/kejilunwen/xinxigongchenglunwen/2201269.html
