极化码的编译码算法研究与FPGA实现

发布时间：2018-12-16 01:21

【摘要】：移动通信系统在过去几十年间发生了翻天覆地的改变,从第一代到第四代移动通信系统,以及即将到来的第五代移动通信系统。移动互联网和物联网的迅速发展将推动5G业务的增长。5G将满足覆盖范围广、容量大、功耗低、广泛连接和延迟低可靠性高的技术场景,这将给产业界带来革命性的变化。信道编码技术作为移动通信中的重要环节,为移动通信系统提供高可靠性的保障。极化码作为新型的信道编码技术,是目前第一个能够通过数学严格证明达到香农容量的信道编码技术,并超越Turbo码和LDPC码的性能。2016年11月17日,在3GPP RAN1 87会议的5G短码方案讨论中,极化码方案最终成为5G eMBB(enhanced Mobile Broadband)场景控制信道编码的最终方案。本文对极化码的编译码算法进行研究,并对其编译码器进行硬件设计与实现,并在FPGA平台上实现编译码器的原型验证。首先本文就信道极化的基本原理进行介绍,从信道合成和信道分裂的角度进行原理阐述,并结合极化现象揭示极化原理的本质。围绕信道极化中的可靠性估计问题给出三种解决方案,对比分析不同估计方法的优缺点,并最终选择高斯近似法作为本文估计的方法。然后本文对极化码的编译码算法进行研究和仿真,对比分析编码算法中系统编码和非系统编码的优缺点,以及译码算法中BP算法,SC算法,SCL算法以及CA-SCL算法的优缺点,并最终选择非系统编码和CA-SCL译码作为硬件设计和实现的算法。基于对算法的分析和研究,本文着重对编译码器进行设计与实现。从硬件模块划分,结构优化的角度进行设计,并给出核心模块的详细接口。从功能仿真的角度进行电路的功能验证,并且在Altera DE5(芯片型号5SGXEA7N2F45C2)上完成电路的原型验证。最后搭建基于PCIE的测试演示系统,从编译码器链路系统的角度完成对编译码器的测试,从而进一步说明电路的正确性和稳定性。本文设计的编码器资源消耗占有率不足1%,最大工作时钟频率610 Mhz,最大吞吐率达到750 Mbps。译码器的资源消耗占有率7%,最大工作时钟频率338Mhz,最大吞吐率达到229.02 Mbps。
[Abstract]:The mobile communication system has undergone tremendous changes in the past few decades, from the first generation to the fourth generation, as well as the upcoming fifth generation mobile communication system. The rapid development of mobile Internet and Internet of things will promote the growth of 5G service. 5G will meet the technology scenarios of wide coverage, large capacity, low power consumption, wide connection and low reliability of delay, which will bring revolutionary changes to the industry. As an important part of mobile communication, channel coding technology provides high reliability guarantee for mobile communication system. Polarization code, as a new channel coding technology, is the first channel coding technology that can strictly prove the Shannon capacity by mathematics, and surpass the performance of Turbo code and LDPC code. In the discussion of 5G short code scheme in 3GPP RAN1 87 conference, the polarization code scheme becomes the final scheme of 5G eMBB (enhanced Mobile Broadband) scene control channel coding. In this paper, the encoding and decoding algorithm of polarization code is studied, and the hardware design and implementation of the codec are carried out, and the prototype verification of the decoder is realized on the FPGA platform. Firstly, the basic principle of channel polarization is introduced in this paper. The principle of channel synthesis and channel splitting is expounded, and the essence of polarization principle is revealed in combination with polarization phenomenon. This paper presents three solutions to the reliability estimation problem in channel polarization, compares and analyzes the advantages and disadvantages of different estimation methods, and finally selects Gao Si approximation as the estimation method in this paper. Then, this paper studies and simulates the encoding and decoding algorithm of polarization code, compares and analyzes the advantages and disadvantages of system coding and non-system coding in coding algorithm, as well as the advantages and disadvantages of BP algorithm, SC algorithm, SCL algorithm and CA-SCL algorithm in decoding algorithm. Finally, non-system coding and CA-SCL decoding are selected as hardware design and implementation algorithms. Based on the analysis and research of the algorithm, this paper focuses on the design and implementation of the codec. From the view of hardware module partition and structure optimization, the detailed interface of the core module is given. The function of the circuit is verified from the point of view of function simulation, and the prototype verification of the circuit is completed on Altera DE5 (chip type 5SGXEA7N2F45C2). Finally, a test demonstration system based on PCIE is built to test the decoder from the point of view of the codec link system, which further explains the correctness and stability of the circuit. The encoder designed in this paper consumes less than 1 bit of resources, and the maximum working clock frequency is 610 Mhz, and the maximum throughput is 750 Mbps.. The decoder has a 7% resource consumption, a maximum clock frequency of 338 MHz, and a maximum throughput of 229.02 Mbps.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22

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