基于PCIe的8通道高速数据采集系统的设计与实现

发布时间：2018-05-16 06:21

本文选题：AD采样 + LVDS　；参考：《郑州大学》2017年硕士论文

【摘要】：在变压器等电压较高的电气设备的绝缘层中会发生局部放电现象,局部放电会导致导体间的绝缘层局部发生短接,对绝缘层的绝缘性能产生影响。轻微的局部放电对绝缘层的绝缘性能影响较小,不会造成绝缘强度的明显下降,但对于强烈的局部放电,绝缘层的绝缘强度很快下降,这会影响设备的安全运行。局部放电是影响变压器稳定性的重要因素,本文基于变压器局部放电信号检测的需要,设计了一种高速数据采集系统,实现局部放电信号的AD采样变换和实时传输,使上位机能够实时接收这些采样数据。本系统分为采样模块和PCIe接口模块两部分,采用XC7K325T FPGA作为系统的控制和处理核心。采样模块将输入的模拟信号进行模数转换后发送给FPGA,在FPGA内部进行串并转换后由FIFO缓存;PCIe接口模块负责将FIFO中的数据组包,并在PCIe用户逻辑的控制下经4-lane PCIe接口传输给上位机。论文重点设计了ADC配置逻辑、串行LVDS接口逻辑和PCIe接口逻辑。ADC配置逻辑实现ADC工作模式的配置;串行LVDS接口逻辑包括位时钟对齐逻辑、框架同步时钟匹配逻辑和串并转换逻辑三部分,实现串行LVDS信号在FPGA内部的正确接收和串并转换;PCIe接口逻辑包括寄存器控制逻辑、发送引擎和接收引擎,实现上位机控制命令的下传和采样数据的上传。通过仿真和调试,采样模块的8个通道能以100MSPS采样速率对信号进行采样,FPGA能正确接收到采样数据,4-lane PCIe接口传输速率为1500M/S,能将采样数据实时传输给上位机。
[Abstract]:Partial discharge will occur in the insulation layer of electrical equipment with high voltage such as transformer. Partial discharge will lead to the partial connection between conductors, which will affect the insulation performance of the insulation layer. The slight partial discharge has little effect on the insulation performance of the insulation layer, and will not cause the obvious decrease of the insulation strength. However, for the strong partial discharge, the insulation strength of the insulation layer will decrease quickly, which will affect the safe operation of the equipment. Partial discharge is an important factor affecting transformer stability. Based on the need of transformer partial discharge signal detection, a high-speed data acquisition system is designed to realize AD sampling conversion and real-time transmission of partial discharge signal. This enables the upper computer to receive these sampled data in real time. The system is divided into two parts: sampling module and PCIe interface module. XC7K325T FPGA is used as the control and processing core of the system. The sampling module transmits the input analog signal to FPGA after analog-to-digital conversion. After serial and parallel conversion in FPGA, the FIFO cache is responsible for the data group packet in FIFO, and it is transmitted to the host computer via 4-lane PCIe interface under the control of PCIe user logic. This paper focuses on the design of ADC configuration logic, serial LVDS interface logic and PCIe interface logic .ADC configuration logic to realize the configuration of ADC mode, the serial LVDS interface logic includes bit clock alignment logic. The frame synchronous clock matching logic and serial-parallel conversion logic are used to realize the correct reception of serial LVDS signals in FPGA and the serial parallel conversion logic including register control logic, sending engine and receiving engine. The control command of upper computer is transmitted down and the sample data is uploaded. Through simulation and debugging, the 8 channels of the sampling module can sample the signal at the 100MSPS sampling rate. The sampling data can be correctly received by the 4-lane PCIe interface transmission rate of 1500 m / s, and the sampling data can be transmitted to the upper computer in real time.
【学位授予单位】：郑州大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP274.2

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