基于FPGA的分数阶PI~λD~μ控制器研究与实现

发布时间：2019-01-14 08:04

【摘要】：基于微处理器实现的数字PID(或者PI~λD~μ)控制器改变了传统的模拟控制器不灵活的问题,但微处理器的复位时间长(达到ms级)以及现场环境恶劣的情况下易出现程序跑飞的问题,影响了控制系统的稳定性和可靠性。FPGA特有的架构可有效提高处理器的运行速度和复位时间,为分数阶PI~λD~μ控制器的实现提供一种有效的方法。针对分数阶PI~λD~μ控制器的数学表达式复杂,不易编程实现的问题,文中将分数阶PI~λD~μ控制器的表达式变形为矩阵相乘的形式,充分利用FPGA架构中的查找表即根据输入地址得到输出数据(数据是预先计算后存入查找表),该算法可以提高分数阶PIλIμ控制器的计算速度和精度。论文采用Modelsim仿真,结果表明该算法实现精度的相对误差小于0.3%,相对于传统的方法具有较大的提高。构建速度闭环控制系统来验证分数阶PI~λD~μ控制器的性能。FPGA中实现的逻辑电路模块主要包括电机测速模块、PWM波产生模块和分数阶PI~λD~μ控制器模块。在电机测速模块中,为了提高速度的测量精度和系统的动态性能,提出动态估算法实现电机的速度测量,针对控制信号的上升沿到第一个被测脉冲上升沿之间的不完整被测脉冲,利用小数估计不完整被测脉冲的思想,用前一个相邻完整脉冲来估算不完整被测脉冲值;利用直接数字合成技术(DDS)输出锯齿波作为载波产生PWM波进而控制电机;分数阶PI~λD~μ控制器主要由寄存器模块、查找表模块、计算系数矩阵A模块和控制模块等。论文对研究内容进行编程并仿真验证,结果表明各模块的功能均达到了预计目标,速度测量结果的输出滞后时间小于2us,实现了电机测速的高精度特征。本文研究与设计了分数阶PI~λD~μ控制器和基于动态估算法测量电机转速,具有提高分数阶PI~λD~μ控制器的计算和速度测量的精度,减少分数阶PI~λD~μ控制器的计算时间和速度测量延迟等特点,有效提高了控制系统的动态性能,为分数阶PI~λD~μ控制器提供一种实现方法,具有较高的工程应用价值。
[Abstract]:The digital PID (or PI~ 位 D ~ 渭) controller based on microprocessor has changed the traditional analog controller's inflexibility. However, the reset time of the microprocessor is long (up to ms level) and the problem of program running is easy to occur when the field environment is bad. The stability and reliability of the control system are affected. The unique architecture of FPGA can effectively improve the speed and reset time of the processor, and provide an effective method for the implementation of fractional order PI~ 位 D 渭 controller. Aiming at the problem that the mathematical expression of fractional order PI~ 位 D 渭 controller is complex and difficult to be realized by programming, the expression of fractional order PI~ 位 D 渭 controller is deformed into matrix multiplying form in this paper. By making full use of the look-up table in FPGA architecture, that is to say, the output data is obtained according to the input address (the data is stored in the look-up table), the algorithm can improve the calculation speed and accuracy of the fractional PI 位 I 渭 controller. The Modelsim simulation results show that the relative error of the algorithm is less than 0.3, which is higher than that of the traditional method. A speed closed loop control system is constructed to verify the performance of fractional order PI~ 位 D 渭 controller. The logic circuit modules implemented in FPGA mainly include motor speed measurement module, PWM wave generation module and fractional order PI~ 位 D 渭 controller module. In order to improve the accuracy of speed measurement and the dynamic performance of the system in the motor speed measurement module, a dynamic estimation method is proposed to realize the speed measurement of the motor. In view of the incomplete measured pulse between the rising edge of the control signal and the first measured pulse, the idea of estimating the incomplete measured pulse is used to estimate the incomplete measured pulse by the previous adjacent complete pulse. The direct digital synthesis technique (DDS) is used to output sawtooth wave as carrier to generate PWM wave and control motor. The fractional order PI~ 位 D 渭 controller is mainly composed of register module, lookup table module, calculation coefficient matrix A module and control module. The results show that the function of each module has reached the expected goal, and the output lag time of the velocity measurement result is less than 2 us. the high precision characteristic of motor speed measurement is realized. In this paper, the fractional-order PI~ 位 D渭 controller and the motor speed measurement based on dynamic estimation method are studied and designed, which can improve the accuracy of calculation and velocity measurement of fractional order PI~ 位 D渭 controller. The dynamic performance of the control system is improved effectively by reducing the calculation time and velocity measurement delay of the fractional order PI~ 位 D 渭 controller. It provides a realization method for the fractional order PI~ 位 D 渭 controller and has high engineering application value.
【学位授予单位】：安徽理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP273

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