高速高精多通道数控系统中基于FPGA的EtherCAT主站设计

发布时间：2018-03-28 23:07

本文选题：EtherCAT　切入点：FPGA　出处：《合肥工业大学》2017年硕士论文

【摘要】：计算机、微电子技术的日新月异使得各行各业经历了变革性的洗礼,在制造业具有举足轻重地位的数控技术也赶上了这时代的潮流,突破了原有的格局,朝着开放多通道式、网络互联化、智能化发展,而数控系统的传统通信接口的弱实时性、复杂的现场配置、固件升级困难等缺陷渐渐成为制约其向高速高精多通道发展的障碍。目前,以太网技术在工业领域中崭露头角,越来越多的数控系统通信接口结合了以太网技术,EtherCAT(Ethernet for Control Automation Technology)工业实时以太网由德国倍福推出,将以太网技术执行到了底层设备级,更兼具了高传输速率、高同步性、低延时、多拓扑等特性。针对数控技术中的通信接口问题,本文提出了基于FPGA实现实时以太网EtherCAT主站的设计方案。首先,结合数控系统的发展状况查阅现场总线的发展历史,指出传统数控系统通信接口的局限性,并提出新的要求。研究近年来出现的实时以太网现场总线的技术背景和国际标准,通过对比主流的实时以太网解决方案,阐述EtherCAT在自动化加工、数控领域中表现出的技术优势。其次,深入研究EtherCAT技术的协议原理,包括拓扑结构、寻址方式、分布式时钟同步原理、应用层协议等,为实现EtherCAT主站做好理论基础。根据研究背景,对主站整体方案实现进行规划和设计。根据主站需求,设计了以FPGA为核心的硬件电路,分别阐述了各个功能模块的设计选型并附有原理图,为主站的实现提供了可靠有效的实现平台。再次,FPGA作为EtherCAT主站实现的主体平台,协议栈主体、网卡驱动等NIOSⅡ软核中实现,其他配合模块以VHDL实现。提出一种亦基于FPGA的以太网现场总线的时钟同步策略和双网口的硬件冗余提高可靠性和处理异警情况的措施的设计思路,基于FPGA可以更加精确的实现时间戳的捕获的特性;利用PI控制器原理建立时钟同步算法并构建时钟频率补偿模块以优化稳定主时钟晶振。利用双网口的硬件结构实现主站的冗余,提高系统可靠性,并给出了从站异常状态下主站的处理流程。最后,构建系统测试平台,包括EtherCAT的FPGA主站控制器,台达数字交流伺服驱动器ASDA-A2-E750W和电机ECMA-C10807RS。通过测试实验表明,以本文设计主站主导的EtherCAT通信系统具有良好的实时性、同步性及稳定性。
[Abstract]:With the rapid development of computer and microelectronics technology, various industries have experienced a revolutionary baptism. Numerical control technology, which plays an important role in the manufacturing industry, has also caught up with the trend of the times, breaking through the original pattern and moving towards the open multi-channel mode. Network interconnection, intelligent development, and the traditional communication interface of CNC system, such as weak real-time, complex field configuration, difficulty in firmware upgrade, etc, gradually become the obstacle to the development of high-speed and high-precision multi-channel. Ethernet technology is emerging in the industrial field. More and more CNC system communication interfaces combine Ethernet technology with Ethernet for Control Automation technology. Industrial real-time Ethernet is introduced by Germany, and the Ethernet technology is executed to the bottom device level. It also has the characteristics of high transmission rate, high synchronization, low delay, multi-topology and so on. Aiming at the problem of communication interface in numerical control technology, this paper proposes a design scheme of real-time Ethernet EtherCAT master station based on FPGA. According to the development of CNC system, the history of fieldbus is consulted, the limitation of communication interface of traditional NC system is pointed out, and the new requirements are put forward. The technical background and international standard of real-time Ethernet fieldbus are studied in recent years. By comparing the mainstream real-time Ethernet solutions, this paper expounds the technical advantages of EtherCAT in the field of automatic machining and numerical control. Secondly, the protocol principle of EtherCAT technology, including topology structure and addressing method, is studied in depth. The principle of distributed clock synchronization, application layer protocol and so on, are used to lay the theoretical foundation for the realization of EtherCAT master station. According to the research background, the overall scheme of master station is planned and designed. According to the demand of master station, the hardware circuit based on FPGA is designed. The design and selection of each functional module are described and the schematic diagram is attached. The realization of the main station provides a reliable and effective implementation platform. Again, as the main platform of EtherCAT master station, the protocol stack main body, network card driver and other NIOS II soft core are realized. Other cooperation modules are implemented by VHDL. A design idea of clock synchronization strategy of Ethernet fieldbus based on FPGA and hardware redundancy of double network port to improve reliability and deal with abnormal alarm situation is presented. Time stamp capture can be realized more accurately based on FPGA. The clock synchronization algorithm is established by using Pi controller principle and the clock frequency compensation module is constructed to optimize and stabilize the master clock crystal oscillator. The redundancy of the master station is realized by using the hardware structure of the double network port and the system reliability is improved. Finally, the system test platform, including EtherCAT FPGA master controller, Delta digital AC servo driver ASDA-A2-E750W and motor ECMA-C10807RS, is constructed. The design of EtherCAT communication system with master station in this paper has good real-time, synchronization and stability.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TG659

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