基于FPGA的Adaboost人脸检测算法设计与验证

发布时间：2017-12-31 18:16

本文关键词：基于FPGA的Adaboost人脸检测算法设计与验证　出处：《东南大学》2017年硕士论文　论文类型：学位论文

更多相关文章： 人脸检测 Adaboost算法 FPGA

【摘要】：人脸识别技术一直以来都是人工智能领域的研究热点之一,并且随着计算方法和计算工具的进步得到了极大地发展。人脸检测作为人脸识别系统的第一步,其检测率和检测速度直接影响整个人脸识别系统的性能,因此实现快速准确的人脸检测系统具有十分重要的意义。本文的主要研究内容是对Adaboost人脸检测算法进行优化设计,使其适用于FPGA平台实现。通过对基于Haar特征的人脸检测算法进行深入分析,确定优化改进方案,在保证检测率的基础上实现人脸的快速检测。本文采用图像缩放和多尺寸检测窗相结合的方法,避免了传统方法对检测窗的非整数倍放大,便于FPGA电路快速实现。为进一步加快检测速度,加大检测窗每次移动的步长,减少检测次数。本文采用小尺寸固定窗对图像进行遍历,以节省存储空间的使用。设计了固定窗积分图计算与存储策略,进一步提高了检测速度。为了降低算法的误检率,对初次检测到的人脸位置进行快速扩展验证。此外本文还采用了平方特征阈值比较方法和浮点数定点化设计,使算法适用于FPGA硬件平台实现。本文基于Opal Kelly公司的开发板XEM6310-LX150完成了 Adaboost人脸检测算法的FPGA电路优化设计和测试验证。实验结果表明,在FPGA系统工作频率62MHz下,人脸检测算法占用Xilinx Sparten-6 系列 XC6SLX150 型 FPGA 上 Slice 资源 1843 个(8%)和片上 RAM 资源 1495Kb(31%)。本文设计人脸检测系统的误检率低于2%,对于包含一张人脸的高清图像(1280×720)的检测率为98%,检测速度为1.96帧/秒,与已知人脸检测系统相比,检测率和检测速度的综合性能更优;对于包含5张人脸图像的检测率为92.56%,检测速度为1.28帧/秒。本文设计的人脸检测系统可以为人脸识别模块快速准确地提供人脸图像信息,进而构建完整人脸识别系统。
[Abstract]:Face recognition technology has always been one of the research hotspots in the field of artificial intelligence, and with the development of computing methods and computing tools, face detection is the first step of face recognition system. The detection rate and detection speed directly affect the performance of the whole face recognition system. Therefore, it is very important to realize a fast and accurate face detection system. The main research content of this paper is to optimize the design of Adaboost face detection algorithm. Make it suitable for the implementation of FPGA platform. Through the in-depth analysis of face detection algorithm based on Haar features, determine the optimized improvement scheme. On the basis of ensuring the detection rate, the face detection is realized quickly. In this paper, the method of image scaling and multi-size detection window is used to avoid the traditional method of non-integer magnification of the detection window. In order to further accelerate the detection speed, increase the step size of each move of the detection window, reduce the detection times. This paper uses a small fixed window to traverse the image. In order to save storage space, a fixed window integral graph calculation and storage strategy is designed to further improve the detection speed. In order to reduce the error rate of the algorithm. In addition, the square feature threshold comparison method and floating-point fixed-point design are used. The algorithm is suitable for the implementation of FPGA hardware platform. This paper is based on the development board XEM6310-LX150 of Opal Kelly. FPGA circuit optimization design and test verification of Adaboost face detection algorithm. Experimental results show that. The operating frequency of FPGA system is 62 MHz. Face detection algorithm occupies 1 843 Slice resources on Xilinx Sparten-6 series XC6SLX150 FPGA.). And on-chip RAM resource 1495kb / 31. the false detection rate of the face detection system designed in this paper is less than 2%. For a high-definition image containing a face 1280 脳 720), the detection rate is 98 and the detection speed is 1.96 frames / sec, which is compared with the known face detection system. The comprehensive performance of the detection rate and the detection speed is better; For five face images, the detection rate is 92.56 and the detection speed is 1.28 frames / sec. The face detection system designed in this paper can provide face image information quickly and accurately for the face recognition module. Then a complete face recognition system is constructed.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP391.41;TN791

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