Turbo编译码方案研究与实现

发布时间：2018-01-01 15:02

本文关键词：Turbo编译码方案研究与实现　出处：《东南大学》2017年硕士论文　论文类型：学位论文

【摘要】：Turbo信道编译码技术从1993年被发现之后,以其卓越的纠错性能,引起了业界的广泛关注,并在诸多的通信系统中得到了应用。本文研究如何将Turbo码与等重编码结合来实现亮度可调可见光通信(D-VLC)系统中的亮度调节问题、Turbo码的并行交织器实现方案以及并行译码方案,并详细介绍了并行译码算法的FPGA设计与实现。论文主要工作如下,一、提出了一种将Turbo码与等重编码结合的方式调节D-VLC系统亮度的方案。在RM码、Turbo码调节D-VLC系统亮度的基础上,提出了一种将Turbo码与等重编码结合的方式调节D-VLC系统亮度的方案。该方案是将Turbo码打孔之后的码流进行等重编码,然后根据亮度级别调节等重编码的码重,从而达到调节系统亮度的目的。此外,该方案不需要利用填充符号来调节亮度,提高了系统传输效率。仿真结果表明,本文提出的系统亮度调节方案虽然在译码复杂度上有所增加,却降低了误比特率,增大了亮度可调范围。二、提出了两种可用于Turbo编码器的新并行交织器。第一种交织器是用时空置换交织(TSP)思想,加上编码匹配交织与S随机交织的约束条件所形成;该交织器加大了 Turbo码的自由距离,提升了译码性能;仿真结果表明该交织器在某些编码长度上能获得比QPP交织器更好的译码性能。第二种并行交织器则是利用TSP思想,加上互素(RP)准则所形成;该交织器在时间置换(行内置换)中使用RP准则,在空间置换(行间置换)中使用随机参数的RP准则,生成方法简单、硬件实现存储量少;仿真结果表明该交织器经过简单筛选后译码性能可以超过QPP交织器。三、基于全并行Turbo译码架构提出了一种改进的并行译码架构——窗并行译码架构。该译码架构结合了传统的滑窗分段译码和全并行译码方式,在译码时,一个译码单元处理一个固定长度码字,并且相邻译码单元之间互相提供信息;仿真结果表明该架构要比全并行译码架构的误比特率性能提升0.2dB。此外,还提出了 Turbo译码中Log-MAP算法模块的改进方案,该方案考虑了数据的动态范围,减小了计算误差,仿真结果表明该方案提升了译码性能。四、介绍了基于窗并行译码架构的FPGA实现,内容包括:并行编码器的实现,编码中并行交织器设计,译码中FPGA中位宽的选取以及各中间计算单元模块、并行QPP交织器模块和最终译码模块的实现。
[Abstract]:Turbo channel coding technology since 1993 were found, with its excellent performance, has aroused widespread concern in the industry, and has been applied in many communication systems. This paper studies how to integrate the Turbo code and re encoding combined to achieve adjustable brightness of visible light communication (D-VLC) system in the regulation of brightness parallel Turbo codes, interleaver scheme and parallel decoding scheme, and introduces the design and implementation of FPGA parallel decoding algorithm. The main work is as follows. First, put forward a kind of Turbo codes and other heavy encoding combination regulation of D-VLC system. In the brightness of the RM code, Turbo code based D-VLC regulation the brightness of the system, put forward a kind of Turbo codes and other heavy encoding combination regulation of D-VLC system project of luminance. The program is the Turbo code stream after drilling and other heavy encoding, then according to the brightness level Don't adjust code heavy encoding, so as to achieve the purpose of adjusting the brightness of the system. In addition, this scheme does not require the use of filling symbols to adjust the brightness, improve the transmission efficiency of the system. The simulation results show that the proposed system brightness adjusting scheme while the decoding complexity is increased, but reduced the error bit rate. Increase the brightness adjustable range. Two, put forward two which can be used in parallel Turbo encoder interleaver. The first interleaver is interleaved with space-time replacement (TSP), plus, interleaving and constraint S encoding random interleaving formed; the interleaver has increased the free distance of Turbo codes. Improve the decoding performance; the simulation results show that the interleaver can obtain the decoding performance of interleaver is better than QPP in some encoding length. Second parallel interleaver is to use the idea of TSP, plus the coprime (RP) formed by the mixed criterion; In the time of replacement (line replacement) using RP criteria in space replacement (row replacement) using random parameters RP criterion, method of generating simple hardware implementation, less storage; the simulation results show that the interleaver after a simple screening decoding performance can be more than QPP intertwined. Three, parallel Turbo decoding the architecture presents an improved parallel decoding architecture of parallel decoding architecture based on windows. The decoding architecture combines the traditional sliding window segmentation decoding and full parallel decoding method in decoding, a decoding unit with a fixed length code words, and provide mutual information between adjacent decoding unit; the simulation results show that the bit error the rate of performance improvement of 0.2dB. in addition to the structure than full parallel decoding architecture, improved scheme of Log-MAP algorithm in Turbo decoding module was proposed, this scheme takes into account the dynamic range of data, reduce the computation Error, the simulation results show that this scheme improves the decoding performance. Four, introduced including the contents of the realization of FPGA window parallel decoding architecture based on encoder implementation of parallel design of parallel interleaved encoding, decoding from FPGA and the middle bit computing unit module, parallel QPP implementation of interleaver module and final decoding module.

【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22

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