分层全并行QC-LDPC码译码器的研究与实现

发布时间：2018-01-07 15:14

本文关键词：分层全并行QC-LDPC码译码器的研究与实现　出处：《华侨大学》2017年硕士论文　论文类型：学位论文

更多相关文章： QC-LDPC码 分层 最小和算法 FPGA CCSDS

【摘要】：LDPC码是一类逼近香农极限(信道容量)的编码,具有很强的纠错能力,被广泛应用在现代通信系统中。由于其优异的译码性能及其编、译码器可以实现高吞吐量,现已成为5G通信中的编码标准。本文结合理论分析和硬件仿真测试,对国际空间数据系统咨询委员会(Consultative Committee for Space Data Systems,CCSDS)建议的QC-LDPC码的编、译码进行研究,并建立了包含编码、调制、加噪、解调、量化和译码等功能模块在内的一套完整的仿真系统。为了兼顾硬件复杂度和吞吐量,采用了分层最小和译码算法(Layered Min-Sum Decoding Algorithm,LMSDA)作为本设计译码器的实现方案。针对传统部分并行结构的资源消耗量大和利用率低等问题,优化设计了一种低复杂度分层全并行(Layered Full-Parallel,LFP)结构的译码器,极大地减少了存储单元的使用。分层全并行结构译码器主要由输入输出缓冲、消息处理单元(MPU)、信息存储和顶层控制等模块组成。在硬件资源上,后验概率信息和信道初始化信息共用一个存储模块,降低了一半存储空间的占用;同时垂直方向上的消息传递由MPU来完成,省去了变量节点模块(VNU)的硬件开销。在性能上,关键模块MPU采用流水线结构化设计,缩短了关键路径的延迟,从而实现了更高的系统工作频率;MPU以及输入/输出缓存模块采用内置状态机,简化了顶层控制模块的设计,译码器整体的延迟得到了降低;各个分层之间采用相对偏移的方式,实现了分层的全并行更新,从而提高了译码吞吐量;同时,LMSDA算法加速了译码迭代的收敛,进一步提高了吞吐量。仿真及硬件测试结果证明,本设计分层全并行LDPC码译码器在工作频率为302.7MHz,10次迭代的情况下,吞吐量可达473.2Mbps,而资源消耗不足传统部分并行结构的1/4。
[Abstract]:LDPC codes are a class of Shannon limit approaching (channel capacity) encoding, with strong error correcting ability, is widely used in modern communication system. Due to its excellent decoding performance and its coding, decoder can achieve high throughput, has now become the standard encoding in 5G communication. This paper combines theoretical analysis and hardware simulation test and on the International Consultative Committee for space data system (Consultative Committee for Space Data Systems, CCSDS) of the proposed QC-LDPC codes encoding and decoding are studied, and the establishment includes encoding, modulation, demodulation, noise, a complete set of simulation system of quantization and decoding functions module. In order to take into account the hardware complexity and throughput that uses a hierarchical minimum sum decoding algorithm (Layered Min-Sum Decoding Algorithm, LMSDA) as the implementation scheme of the decoder. The traditional parallel structure of resource consumption And the low utilization rate, design a low complexity layered parallel (Layered Full-Parallel LFP) decoder, greatly reducing the use of storage unit. The hierarchical parallel decoder structure is mainly composed of input and output buffer, message processing unit (MPU), information storage and control module in the top. The hardware resources, a posteriori information and channel initialization information sharing a memory module, reduces the occupied half storage space; at the same time, the vertical direction of the message transfer completed by MPU, the variable node module is omitted (VNU) hardware overhead. In the performance, the key modules of the MPU pipeline using structured design, shorten the the critical path delay, so as to realize the system of the higher frequency; MPU and input / output buffer module with built-in state machine, simplifies the design of the control module at the top, the whole decoder The delay has been reduced; relative offset mode is used between each layer, to achieve a full parallel hierarchical update, thus improving the decoding throughput; at the same time, the LMSDA algorithm to accelerate the convergence of iterative decoding, to further improve the throughput. Simulation and hardware test results prove that the design of hierarchical parallel LDPC decoder in frequency for 302.7MHz, the 10 iteration under the condition that the throughput of up to 473.2Mbps, while the consumption of resources shortage of traditional partial parallel structure 1/4.

【学位授予单位】：华侨大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22

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