应用于高速高精度Pipelined ADC中电容失配校正算法的研究

发布时间：2018-01-13 22:15

本文关键词：应用于高速高精度Pipelined ADC中电容失配校正算法的研究　出处：《吉林大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着技术的发展,各种应用对ADC(Analog to Digital Converter,模数转换器)的要求也越来越高。在众多的ADC架构中,Pipelined ADC(流水线型ADC)被认为是同时兼具高速度、低功耗、高精度的一种架构。近年来工艺的飞速发展并没有给Pipelined ADC的性能带来很大的提升,主要是因为在Pipelined ADC中影响性能的主要因素是电容失配以及放大器增益不足。放大器增益的不足可以通过增加放大器的级数或者采用Gain-boosting技术来解决;电容失配,可以通过增加电容面积的方法来减小,但这也就意味着功耗的增加。这些都是与消费类电子低功耗的要求相悖的。因此对于电容失配的解决方法,人们更加倾向于通过校正算法来实现。由于数字电路在更小的工艺节点中的优势更加明显,因此校正算法更希望是通过数字电路来实现。校正算法必须包括两个过程,第一是对误差的测量,第二是对ADC输出结果的补偿与校正。根据ADC在使用过程中是否需要一个独立的校正过程,又将校正算法分为前端校正算法和后端校正算法。相较于前端校正算法,后端校正算法由于是实时校正,因此对环境、温度等因素的影响更具有鲁棒性,也更加的智能化。因此ADC中电容失配校正算法更加趋向于后端校正。目前针对于采用1.5-bit/stage MDAC的Pipelined ADC的数字校正技术大都通过注入伪随机码的形式测量误差,并在数字域中对结果进行校正。这种校正算法最大的缺点是注入的随机向量会大大减小ADC的输入范围。相较于1.5-bit/stage MDAC,=2.5bit/stage MDAC在降低对工艺的要求的同时,在功耗上也具有更大的优势。然而目前针对于采用=2.5-bit/stage MDAC的Pipelined ADC中电容失配校正算法的研究多集中于数字前端校正,对于数字后端校正算法则鲜有报道。本课题提出了一种适用于采用2.5-bit/stage MDAC的Pipelined ADC中电容失配的数字后端校正算法,并在MATLAB上对其可行性、准确性、稳定性进行了验证。应用此技术,设计了一款分辨率为14 bits、采样率为40MS/s的Pipelined ADC。本课题采用X-fab 0.18um工艺,进行了电路图的设计与验证,版图的设计与验证,并对芯片进行了测试。芯片整体面积4x4mm2;在3.3V电压下,整体功耗为110m W;芯片的测试结果表明,在2^26个时钟周期内,可将ENOB由10.3 bits提高至12.1 bits。
[Abstract]:With the development of technology, various applications of ADC (Analog to Digital Converter, ADC) are increasingly high requirements. In the ADC architecture, Pipelined ADC (pipliened ADC) is considered to be both high speed and low power consumption, a kind of architecture with high precision. In recent years, the rapid development of technology and not to the performance of Pipelined ADC has greatly improved, mainly because the main factors affecting the performance of Pipelined in ADC is less than the capacitor mismatch and amplifier gain. Insufficient amplifier gain can be solved by increasing the amplifier series or using Gain-boosting technology; capacitor mismatch can be reduced by increasing the area of the capacitor. But this also means that the increase in power. These are contrary to consumer electronics and low power requirements. Therefore, the methods for solving the capacitor mismatch, people are more inclined to the Correction algorithm. Due to the advantages of digital circuit in the process node smaller in more obvious, so the correction algorithm is more hope to achieve through the digital circuit. The correction algorithms must include two stages, the first is to measure the error is second, compensation and correction of the ADC output results. According to whether the ADC is in the process of using the need for a separate correction process, and the correction algorithm is divided into front-end and back-end correction algorithm algorithm. Compared to the front-end back-end correction algorithm, correction algorithm for real-time correction and so on the environment, temperature and other factors is more robust, more intelligent. Therefore ADC capacitor mismatch correction algorithms tend to be more present in the end correction. Using 1.5-bit/stage MDAC Pipelined ADC digital correction technology mostly through the injection form of measurement error of pseudo random code, and in the digital domain The results were corrected. This algorithm is the biggest drawback is the input range of random vector injection will be greatly reduced compared to the ADC. 1.5-bit/stage MDAC, =2.5bit/stage MDAC in reducing the requirement of the process at the same time, also has more advantages in power consumption. However, according to MDAC Pipelined ADC by =2.5-bit/stage in capacitor research with the correction algorithm focused on digital front-end to back-end digital correction, correction algorithm is rarely reported. The number of back-end correction algorithm is proposed in this paper which is suitable for using 2.5-bit/stage MDAC Pipelined ADC capacitor mismatch, and MATLAB on the feasibility, accuracy and stability are verified. The application of this technology. The design of a resolution of 14 bits, sampling rate of 40MS/s Pipelined ADC. using the X-fab 0.18um technology, the design and verification of the circuit diagram, The design and verification of the layout and the chip were tested. The overall area of the chip is 4x4mm2. Under the 3.3V voltage, the overall power consumption is 110m W. The test results of the chip indicate that in the 2^26 clock cycle, ENOB can be increased from 10.3 bits to 12.1 bits..

【学位授予单位】：吉林大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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