40纳米NBTI建模及其可靠性设计研究

发布时间：2018-01-20 07:39

本文关键词： 负偏压温度不稳定性 R-D T/D 参数提取可靠性设计时钟偏移　出处：《华东师范大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着晶体管尺寸的不断缩小,负偏压温度不稳定性(Negative Bias Tenperature Instability,NBTI)已经成为制约电路可靠性最重要的因素。本论文基于40nmCMOS工艺对NBTI效应模型参数提取进行研究,并采用VeritogA对模型及参数进行描述,构建NBTI等效电压源元件,最后对时钟网络时钟偏移NBT[退化进行了仿真及分析。主要工作及研究内容如下:1)基于40nm CMOS工艺单管PM0S退化测试数据对NBTI的反应-扩散(R-D)模型以及缺陷捕获/释放(T/D)模型进行了参数提取,提出并建立了(Coarse-Fine)两步参数提取方法。2)基于所提参数编写VerilogA退化模型元件,将其内嵌入Hspice以及Spectre的PDK库中。并采用该元件对NBTI作用下的反向器退化特性进行了仿真分析,结果表明该方法可有效反映门逻辑单元的时域退化特性。3)通过数值仿真对反相器的传输延迟进行建模,并提出一种无门控时钟网络偏移的NBTI退化分析计算方法。基于此方法对基准电路ISCAS85-S38417的时钟网络NBTI退化进行计算,并将其结果与Hspice仿真结果进行比对,结果表明误差约为3.3%,可满足时钟网络退化分析计算需求。同时利用NBTI等效电压源对带门控时钟网络偏移进行了仿真及预测,并根据仿真结果对时钟网络进行了优化。本论文所建模型参数提取方法及电路可靠性设计方法可为高性能高可靠性集成电路设计提供重要依据及参考。
[Abstract]:As the size of the transistor shrinks, the negative bias temperature instability is negative Bias Tenperature Instability. NBTI has become the most important factor that restricts the reliability of the circuit. In this paper, the extraction of NBTI effect model parameters based on 40nm CMOS process is studied. The model and parameters are described by VeritogA, and NBTI equivalent voltage source elements are constructed. Finally, the clock network clock is offset by NBT. [Simulation and analysis of degradation. The main work and research contents are as follows: 1) Reaction-Diffusion R-D) based on 40nm PM0S degradation test data of single-tube PM0S in 40nm CMOS process. The model and the defect capture / release T / D model were used to extract the parameters. A two-step parameter extraction method of Coarse-Fine. 2) is proposed and established. 2) based on the proposed parameters, the VerilogA degradation model elements are compiled. It is embedded in the PDK library of Hspice and Spectre, and the degradation characteristics of the inverter under the action of NBTI are simulated and analyzed by using this element. The results show that this method can effectively reflect the time-domain degradation characteristics of gate logic units. 3) the transmission delay of the inverter is modeled by numerical simulation. A method of NBTI degradation analysis without gating clock network offset is proposed, based on which the NBTI degradation of clock network of reference circuit ISCAS85-S38417 is calculated. The results are compared with the results of Hspice simulation, and the results show that the error is about 3.3%. It can meet the needs of clock network degradation analysis and calculation. At the same time, the offset of clock network with gated control is simulated and predicted by using NBTI equivalent voltage source. According to the simulation results, the clock network is optimized. The model parameter extraction method and the circuit reliability design method can provide important basis and reference for the design of high performance and high reliability integrated circuit.
【学位授予单位】：华东师范大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386

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