实时性容错以太网交换机的电路设计

发布时间：2018-02-11 15:07

本文关键词： 以太网交换机电路算法仿真同步模块　出处：《北京交通大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着通信技术的发展,以太网被广泛应用于航空领域以及工业控制领域。实时性容错以太网将时间触发技术的确定性、容错机制和实时性能,同传统以太网的灵活性、动态性能以及“尽力而为”相结合,为同步的、高度可靠嵌入式网络系统提供支持。本论文研究了实时性容错以太网的通信算法,并完成了交换机电路设计以及功能仿真。主要内容如下文所述:(1)研究了实时性容错以太网的协议体系结构。实时性容错以太网在标准工业以太网802.3协议基础之上,添加了时间同步系统。实时性容错以太网能完成时间触发业务、传统以太网业务以及时间同步算法。(2)研究了实时性容错以太网的时间同步算法。实时性容错以太网通过协议控制帧中携带的时间信息,完成时间同步算法。时间同步算法包括时序保持算法、压缩算法以及时钟矫正算法。(3)本文针对透明时钟的现有测量方法提出了改进方案。现有测量方法仅仅测量出了数据包的链路延迟;本文通过打时间戳的方法,测量出了交换机处理数据包的时间。(4)完成实时性容错以太网交换机的电路设计以及仿真。本文根据实时性容错以太网的传输业务,把交换机设计成三大模块。本文运用Verilog语言实现交换机功能,并通过ModelSim软件仿真出波形图。文本通过对波形图分析,得出如下结论:交换机通过完成时间同步算法,矫正了本地时钟,保证了时间触发业务无误差发送。
[Abstract]:With the development of communication technology, Ethernet is widely used in aviation and industrial control fields. Real-time fault-tolerant Ethernet brings certainty, fault-tolerant mechanism and real-time performance to traditional Ethernet. Dynamic performance and "best effort" are combined to provide support for synchronous and highly reliable embedded network systems. In this paper, the communication algorithm of real-time fault-tolerant Ethernet is studied. The switch circuit design and function simulation are completed. The main contents are as follows: 1) the protocol architecture of real-time fault-tolerant Ethernet is studied. The real-time fault-tolerant Ethernet is based on the standard industrial Ethernet 802.3 protocol. The time synchronization system is added. The real-time fault-tolerant Ethernet can complete the time trigger service. The time synchronization algorithm of real-time fault-tolerant Ethernet is studied in the traditional Ethernet service and time synchronization algorithm. The real-time fault-tolerant Ethernet carries time information in the protocol control frame. Complete time synchronization algorithm. Time synchronization algorithm includes timing retention algorithm, Compression algorithm and clock correction algorithm. This paper proposes an improved scheme for the existing measurement methods of transparent clock. The existing measurement methods only measure the link delay of the data packet. The circuit design and simulation of real-time fault-tolerant Ethernet switch are completed by measuring the time of packet processing in switch. According to the transmission service of real-time fault-tolerant Ethernet, The switch is designed into three modules. The function of switch is realized by using Verilog language, and the waveform diagram is simulated by ModelSim software. By analyzing the waveform diagram, the following conclusions are drawn: the switch completes time synchronization algorithm, Corrects the local clock, guarantees the time trigger service no error transmission.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP393.11

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