基于28nm工艺低电压SRAM单元电路设计

发布时间：2018-03-07 18:12

本文选题：SRAM　切入点：低电压　出处：《安徽大学》2017年硕士论文　论文类型：学位论文

【摘要】：为了满足人们对高性能电子产品日益增长的需求和降低产品的成本达到利益的最大化,半导体的制造工艺节点在持续的缩小,推动集成电路进入后摩尔时代。近年来SOC(片上系统)技术逐渐成为IC设计业界的焦点,SRAM(静态随机存取存储器)作为其必不可少的一部分被集成到SOC芯片中,由于高性能SRAM存储器存在着不可或缺的应用,一直是工业界和学术界研究的热点。SRAM存储器主要包括存储阵列,灵敏放大器,时序控制电路,译码电路和输入输出驱动模块。其中,存储阵列占据着整个存储系统的大部分面积,其性能的优劣直接影响着SRAM存储系统的性能。随着工艺节点和电源电压的下降,器件的阈值电压越来越小,另外,相邻晶体管之间阈值电压的不匹配也越来越明显,导致SRAM存储单元的鲁棒性越来越差。存储单元在工作时,读破坏,半选单元读破坏越来越频繁,写能力也越来越弱,甚至出现读写错误。SRAM存储系统的功耗大部分来自单元操作时的动态功耗和休眠状态时的静态功耗,随着工艺节点的缩小,芯片的静态功耗将会越来越大,甚至超过动态功耗成为芯片的主要功耗。电压的下降可以显著地降低静态功耗和二次方形式的降低动态功耗,低电压下SRAM的设计越来越普遍,在保证单元性能的前提下,可以很好的延长便携式设备的电池寿命。但低电压下,SRAM单元的性能进一步的恶化,如速度的下降,稳定性的恶化,错误率的飙升等;这些,使得传统SRAM单元越来越不能满足我们的需求。本文首先分析研究了 SRAM存储系统的重要性及先进工艺下SRAM单元性能面临的各种挑战。其次在分析传统SRAM存储单元工作原理的基础上,采用VTC蝴蝶曲线,字线电压驱动,位线电压驱动和N曲线方法衡量了其静态噪声容限。在这种背景下,分析研究了前人提出的多种单元优化方法。这些设计方法,大部分仅仅优化了单元读、写一方面的性能,另一方面保持不变或者有恶化的趋势;单端读写单元往往恶化了读写速度,并使灵敏放大器的设计面临挑战;辅助电路的设计,往往会使SRAM的设计复杂化。为了使SRAM存储单元的性能得到整体的提升,本文提出了读写裕度同时提升的新型10TSARM单元电路结构,可以很大程度上抑制传统6T存储单元读操作时"0"节点的分压问题,提高SRAM存储单元的读静态噪声容限(RSNM),进而提升SRAM存储单元的读稳定性。在写操作时,用位线电压提供交叉耦合反相器的电源电压,降低了单元维持"1"的能力和一边反相器的翻转点,这样可以很大程度的提高SRAM存储单元的写裕度(WM)。同时,可以优化SRAM存储单元的抗PVT波动能力,并且可以降低SRAM存储单元的最小操作电压。基于SMIC 28nm工艺节点仿真结果显示,新型10T单元结构在电源电压为1.05V时,和传统6T单元相比,RSNM提升了 2.19倍,WM提升了 2.13倍。同时,在单元读写操作时,错误率较低。另外,新型单元的最小工作电压仅为传统的59.19%,拥有更好的抗工艺变化能力。
[Abstract]:In order to meet the people of high performance electronic products growing demand and reduce the cost of the product to achieve the maximum benefit of the semiconductor manufacturing process, the nodes in the continue to shrink, to promote the integrated circuit after entering the Moore era. In recent years, SOC (system on chip) technology has gradually become the focus of IC design industry, SRAM (static random access memory) as part of its essential is integrated into the SOC chip, the high performance SRAM memory has an application,.SRAM memory has been a hot topic in industrial and academic research mainly includes memory array, sense amplifier, a timing control circuit, decoding circuit and input and output drive module. The storage array occupies the most the area of the storage system, its performance will directly affect the performance of SRAM storage system. With the decline process node and the supply voltage is. More and more small pieces of the threshold voltage, the threshold voltage mismatch between adjacent transistors is becoming more and more obvious, leading to robust SRAM memory cell is getting worse. The storage unit failure at work, read, read half unit failure more frequently, writing ability is more and more weak, even the power of reading and writing the error of.SRAM storage system mostly from static power consumption dynamic power unit operation and a dormant state, as the technology node shrink, the static power consumption will be more and more big chip, even more than the dynamic power consumption has become the main power chip. The voltage drop can significantly reduce the static power consumption and the two party in the form of reducing dynamic power consumption low voltage design, SRAM is more and more common, under the premise of ensuring unit performance, can be very good to prolong the battery life of portable devices. But under low voltage, the performance of SRAM unit in The deterioration of a step, such as the speed of the decline, stability deteriorated, error rate soared; of these, the traditional SRAM unit can not meet the growing demand. We study the various challenges facing the unit performance of SRAM importance SRAM storage system and advanced technology this paper analyzes. Secondly based on the analysis of traditional SRAM storage the working principle of the unit, the VTC butterfly curve, word line voltage, bit line voltage drive and N curve method to measure the static noise margin. In this context, analysis of the multiple unit optimization method proposed by previous researchers. Most of these design methods, optimization of the unit only read and write performance on the one hand on the other hand, remain unchanged or have a tendency to deteriorate; single ended read and write unit often deteriorates the read and write speed, and make the design of sensitive amplifier challenges; auxiliary circuit design, often make the SRAM The design is complex. In order to make the performance of the SRAM storage unit to get the whole promotion, is proposed in this paper to read and write margin and improve the new 10TSARM unit circuit structure, can greatly inhibit the traditional 6T storage unit read "0" node pressure, improve the read static noise margin SRAM storage unit (RSNM), and thus enhance the stability of the SRAM storage unit. Read in write operation, a bit line voltage supply voltage of cross coupled inverters, reduces the turning point unit maintain "1" ability and side inverter, which can greatly improve the SRAM storage unit and write margin (WM) at the same time. PVT, anti wave ability can optimize the SRAM storage unit, the minimum operating voltage and can reduce the SRAM storage unit. SMIC 28nm technology node based simulation results show that the new 10T cell structure in the power supply voltage of 1.05V, and Compared with the 6T unit, the RSNM increased by 2.19 times and the WM increased by 2.13 times. At the same time, the error rate of the cell read and write operation is low. Moreover, the minimum working voltage of the new cell is only 59.19% of the traditional one, and has a better ability to resist technological change.

【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333

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