无线通信网络中CMOS功率放大器的研究与设计

发布时间：2018-03-22 04:31

本文选题：无线通信　切入点：CMOS功率放大器　出处：《中国科学技术大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着无线通信市场的持续繁荣与发展,小尺寸、低成本、低功耗和更加稳定的无线通信设备越来越受到消费者的青睐。CMOS工艺凭借其低成本以及易集成等优势,已经使得大部分的无线收发模块都能在不牺牲性能的前提下采用CMOS工艺实现。然而功率放大器,作为无线收发机中耗能最多、尺寸最大的模块,仍然是尚未被成功集成的几个模块之一。本文基于不同的无线通信应用背景,对CMOS功放的相位和功率控制、可靠性、集成度和功率回退时的效率等几个方面进行了研究。针对超高频RFID中自干扰信号的问题,本文设计了一种相位和幅度可以数字控制的全集成功放。该功放由有源移相电路、缓冲电路和增益可控的功率放大电路组成。文中分析了各个模块的基本原理和电路结构。为了降低数控功放的AM-PM失真,增益可控的功率放大电路采用了一种电容补偿技术。该功放采用130nm CMOS工艺实现,仿真结果表明,数控功放在840MHz～960MHz的工作频段内,相位均方根误差小于0.21°,输出功率变化小于1dBm,取得了较好的相位和幅度控制精度。将该功放应用到自干扰抵消系统,仿真结果显示,功率为8dBm的自干扰信号最大可被抑制38dB。为了满足超高频RFID发射信号的要求,本文设计了一种全集成的线性功放。该功放采用一种带有校准电路的有源巴伦作为驱动级,同时该巴伦又提供了输入信号单端转差分的功能,节约了芯片面积。为了实现功放的全集成,本文还设计了一种可以实现差分转单端功能的片上变压器作为输出匹配网络。该功放在130 nmCMOS工艺下实现,核心面积仅为0.83 mm-_2,仿真结果表明,功放在输出功率为27dBm时,效率能达到41%。为了支持更高的通信速率,现代无线通信信号的调制峰均比越来越高,功放将不可避免地要工作在功率回退状态。为了提高功放在功率回退时的效率,本文在传统负载调制技术的基础上,设计了一种可动态切换的双模功放。文中分析了MOS开关在关断时功率损耗的来源,并在可调匹配网络中采用了一种耐高压的开关电容来减少高输出功率时的功率泄露。通过采用一种功率检测控制电路对功放的偏置、晶体管尺寸和最优负载进行动态调节,功放在功率回退7dB时的效率可提升11.7%。在带宽为40MHz的802.11n OFDM 64-QAM调制信号激励下,功放在输出功率为18dBm时的EVM和ACPR完全符合协议的线性度要求。
[Abstract]:With the continued prosperity and development of wireless communication market, wireless communication devices with small size, low cost, low power consumption and more stability are becoming more and more popular among consumers with the advantages of low cost and easy integration. It has enabled most wireless transceiver modules to be implemented using CMOS technology without sacrificing performance. However, power amplifiers are the most energy-consuming and largest modules in wireless transceivers. It is still one of the several modules that have not been successfully integrated. Based on the different wireless communication application background, the phase and power control and reliability of CMOS power amplifier are discussed in this paper. The integration level and the efficiency of power back time are studied in this paper. Aiming at the problem of self-interference signal in UHF RFID, a digitally controlled full-set amplifier is designed, which is composed of an active phase-shifting circuit. The basic principle and circuit structure of each module are analyzed in this paper. In order to reduce the AM-PM distortion of numerical control power amplifier, the circuit is composed of buffer circuit and gain controllable power amplifier circuit. A capacitive compensation technique is used in the gain controllable power amplifier, which is realized by 130nm CMOS technology. The simulation results show that the power amplifier is in the working frequency band of 840MHz~960MHz. The phase root mean square error is less than 0.21 掳and the output power is less than 1dBm.The phase and amplitude control accuracy is better. The simulation results show that the power amplifier is applied to the self-interference cancellation system. In order to satisfy the requirement of UHF RFID transmission signal, a fully integrated linear power amplifier is designed. The amplifier adopts an active Barron with calibrated circuit as the driving stage, and the self-interference signal with the power of 8dBm can be suppressed at a maximum of 38dB.In order to meet the requirements of the UHF RFID transmission signal, a fully integrated linear power amplifier is designed. At the same time, the Barron also provides the function of single-terminal differential input signal, which saves the chip area, in order to realize the full integration of power amplifier, This paper also designs a kind of on-chip transformer which can realize the function of differential switching single terminal as the output matching network. The power amplifier is realized in 130#en0# process, and the core area is only 0.83 mm-2. The simulation results show that the power amplifier can be used when the output power is 27dBm. Efficiency can reach 41. In order to support higher communication rate, the modulation peak to average ratio of modern wireless communication signal is higher and higher, the power amplifier will inevitably work in the state of power back, in order to improve the efficiency of power amplifier when power back, Based on the traditional load modulation technology, a dynamic switching dual-mode power amplifier is designed in this paper. The source of power loss when the MOS switch is turned off is analyzed. In the adjustable matching network, a high voltage tolerant switch capacitor is used to reduce the power leakage when the output power is high. The bias, transistor size and optimal load of the power amplifier are dynamically adjusted by a power detection control circuit. The efficiency of power amplifier can be improved by 11.7when the power is back 7dB. Under the excitation of 802.11n OFDM 64-QAM modulation signal with bandwidth 40MHz, the EVM and ACPR when the output power is 18dBm fully meet the linearity requirement of the protocol.
【学位授予单位】：中国科学技术大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN722.75

【参考文献】