高精度可调节模拟延迟线设计

发布时间：2018-06-29 12:49

本文选题：相控阵天线 + 模拟延迟单元　；参考：《东南大学》2017年硕士论文

【摘要】：相控阵天线技术自出现以来,在雷达和通信等领域得到了广泛的应用。近年来,随着信息的高速发展,军用和民用的需求不断提高,对相控阵天线性能的要求也越来越高。传统相控阵天线受到扫描角度、孔径效应以及有限瞬时带宽的限制,很难满足相控阵天线在高性能领域的应用。相比于传统移相器,基于实时延迟技术(TTD)的非色散可变延迟线能够有效的抵消孔径渡越时间的影响,使得相控阵天线能够满足宽带、宽扫描角的要求。基于CMOS工艺的实时延迟线,具有低功耗、低成本以及高集成度的优势。作为相控阵天线的关键模块,实时延迟线的设计实现至关重要。本文设计了一种高精度可变模拟实时延迟线。基于无源和有源延迟单元相结合的技术以提高电路的信号增益,优化电路面积。整个电路结构分为三部分,包括粗调节有源延迟模块、级间匹配模块以及细调节无源延迟模块。粗调节有源延迟模块包括有源延迟单元和模拟路径选择开关构成,通过数字电路控制模拟开关的导通状态实现信号路径的选择;级间匹配电路用来实现无源电路与有源电路之间的匹配;无源延迟模块通过电压控制可变电容的大小实现连续可调的细调节延迟。整体实现了小面积、低功耗、大范围、高集成度的可调节模拟实时延迟线。本设计采用TSMC0.18μm CMOS工艺,芯片总面积为690×900μm2。后仿真结果表明,在0.5GHz-3.1GHz的频率范围内,实时延迟线在TT工艺角下可实现0～91ps的连续相对延迟。总延迟范围包含3级有源延迟单元的延迟以及无源延迟单元的延迟,单级有源延迟单元可实现22ps的平均延迟,细调节无源延迟整体实现25ps的连续延迟。在不同工艺角下整体电路增益抖动小于±2.1dB,最大延迟抖动为4.9%。在1.8V的供电电压下电路功耗为25.6mW。
[Abstract]:Since the emergence of phased array antenna technology, it has been widely used in radar and communication fields. In recent years, with the rapid development of information, the demand of military and civilian is increasing, and the performance of phased array antenna is becoming more and more important. The traditional phased array antenna is limited by scanning angle, aperture effect and limited instantaneous bandwidth, so it is difficult to satisfy the application of phased array antenna in the field of high performance. Compared with the traditional phase shifter, the non-dispersive variable delay line based on real time delay (TTD) can effectively counteract the influence of aperture transit time, so that the phased array antenna can meet the requirements of wideband and wide scanning angle. Real-time delay lines based on CMOS technology have the advantages of low power consumption, low cost and high integration. As the key module of phased array antenna, the design and realization of real-time delay line is very important. In this paper, a high precision variable analog real-time delay line is designed. In order to improve the signal gain and optimize the circuit area, the passive and active delay cells are combined to improve the signal gain of the circuit. The whole circuit structure is divided into three parts, including coarse regulation active delay module, inter-stage matching module and fine-tuning passive delay module. The coarse regulating active delay module consists of an active delay unit and an analog path selection switch. The signal path selection is realized by controlling the on-state of the analog switch by digital circuit. The inter-stage matching circuit is used to match the passive circuit with the active circuit, and the passive delay module realizes the continuously adjustable fine adjustment delay through the voltage control of the variable capacitance. Small area, low power consumption, large range, high integration and adjustable real time delay line are realized. This design uses TSMC 0.18 渭 m CMOS technology, the total area of the chip is 690 脳 900 渭 m 2. The simulation results show that in the frequency range of 0.5GHz to 3.1GHz, the continuous relative delay of 0~91ps can be realized at the angle of TT process. The total delay range includes the delay of the three-stage active delay unit and the passive delay unit. The single-stage active delay unit can realize the average delay of the 22ps and the fine adjustment of the passive delay can realize the continuous delay of the 25ps. The gain jitter of the whole circuit is less than 卤2.1 dB and the maximum delay jitter is 4.9 under different process angles. The power consumption of the circuit is 25.6 MW at 1.8 V supply voltage.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN821.8

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