薄层SOI高压LDMOS背栅调制模型与特性研究

发布时间：2017-12-28 04:22

本文关键词：薄层SOI高压LDMOS背栅调制模型与特性研究　出处：《电子科技大学》2016年博士论文　论文类型：学位论文

【摘要】：SOI(Silicon On Insulator,绝缘体上硅)高压LDMOS(Lateral Double-diffused Metal Oxide Semicondutor,横向双扩散金属氧化物半导体)器件因其低功耗、高频率、高集成度等特点,广泛用于汽车电子、医疗电子、智能家电和航空航天等智能功率集成电路。相比厚层SOI结构,薄层SOI LDMOS具有良好的工艺兼容性和较少的寄生效应,在功率集成电路,特别是功率开关和驱动集成电路中有着良好的应用前景。但是由于背栅效应,薄层SOI LDMOS器件性能和可靠性受到严重影响,尤其是p沟道LDMOS。目前背栅效应研究主要集中于对器件击穿电压的影响,对比导通电阻、甚至可靠性的影响鲜有报道。负偏置温度不稳定性(Negative Bias Temperature Instability,简称NBTI)是p沟道MOS器件最重要的可靠性问题之一,SOI高压器件埋氧层长期受到背栅偏置影响,其背栅NBTI效应会对器件特性产生影响。然而目前NBTI研究主要针对栅氧化层,对于SOI器件埋氧层研究未见报道。本论文围绕背栅效应,基于场荷调制理论,研究了薄层SOI高压场p沟道LDMOS比导通电阻、击穿电压特性和陷阱电荷诱致退化效应。提出背栅场调制耐压模型,揭示了背栅对击穿电压和比导通电阻影响机理。体内电场受到背栅电压调制,引起体内电荷分布变化,形成双导电模式,极大改善了击穿电压与比导通电阻关系。提出陷阱电荷电导调制模型,揭示了器件背栅NBTI和热载流子退化机理。背栅NBTI和热载流子效应产生的场致陷阱电荷引起体内电荷分布变化,从而导致器件特性发生退化。主要创新点如下:1.提出背栅场调制耐压模型基于场荷调制理论,提出背栅场调制耐压模型,揭示了薄层SOI高压场p沟道LDMOS背栅电压对击穿电压和比导通电阻影响机理,给出了背栅电压与表面击穿电压、比导通电阻之间关系。体内电场受到背栅电压调制,导致表面击穿电压与背栅电压呈线性关系:BVs=0.98×VBG 198.4。同时调制体内场引起体内电荷分布变化,形成双导电模式,使得器件比导通电阻Ron,sp取决于漂移导电层和积累导电层并联的结果:Ron,sp=1/(1.45×10-13 ts ND 7.07×10-4 VBG),极大地改善了击穿电压与比导通电阻的关系。2.提出背栅穿通判据和器件耐压设计准则提出背栅穿通判据,揭示器件背栅穿通机理,可适用于所有SOI p沟道LDMOS器件。提出SOI高压场p沟道LDMOS器件耐压设计准则,即电源电压VHV|BVs(VBG=VHV)|,|BVb|和|BVp|,同时考虑了漏极电压与背栅电压。实验结果显示,器件击穿电压达到-366 V,比导通电阻仅为6.6Ω?mm2。基于研究结果,首创目前国际集成场p LDMOS的最薄导电硅层系列SOI高低压兼容工艺,并在国防装备得到应用,取得良好的社会和经济效益。3.提出薄层SOI高压场p沟道LDMOS陷阱电荷电导调制模型提出陷阱电荷电导调制模型,揭示了薄层SOI高压场p沟道LDMOS背栅NBTI和热载流子引起线性电流退化的机理。背栅NBTI和热载流子效应的场致陷阱电荷引起漂移区和沟道电荷发生变化,从而导致线性电流退化。背栅NBTI在埋氧层产生总正的场致陷阱电荷,降低体内积累层电荷密度、击穿点处电场峰值和能带,导致线性电流降低、击穿电压和静态电流增加。两种相反的热载流子效应机理共同决定了线性电流退化:沟道区里的热空穴注入产生正的陷阱电荷,导致阈值增加,线性电流降低;漂移区栅极场板末端的热电子注入产生负的陷阱电荷,导致线性电流增加。
[Abstract]:SOI (Silicon On Insulator, silicon on insulator) high voltage LDMOS (Lateral Double-diffused Metal Oxide Semicondutor, lateral double diffused metal oxide semiconductor) devices due to its low power consumption, high frequency, high integration and so on, are widely used in automotive electronics, medical electronics, aerospace and other smart appliances and smart power integrated circuit. Compared with the thick SOI structure, thin layer SOI LDMOS has good process compatibility and less parasitic effect. It has a good application prospect in power integrated circuits, especially in power switches and driving integrated circuits. However, due to the back gate effect, the performance and reliability of thin layer SOI LDMOS devices are seriously affected, especially the P channel LDMOS. At present, the research on the back gate effect is mainly focused on the impact of the breakdown voltage on the device, and there are few reports on the effect of comparing the resistance and even the reliability. Negative Bias Temperature Instability (referred to as NBTI) is one of the most important reliability problems of P channel MOS devices. The oxide layer of SOI high voltage device is influenced by back grid bias for a long time, and its back gate NBTI effect will have an impact on device characteristics. However, at present, the study of NBTI mainly focuses on the gate oxide layer, and there is no report on the study of the embedded oxygen layer of SOI devices. Focusing on the back gate effect, based on the field charge modulation theory, the P channel LDMOS specific conduction resistance, breakdown voltage characteristics and trap induced degradation effect of thin SOI high voltage field are studied. A back gate field modulated pressure resistance model is proposed, and the influence mechanism of the back gate on the breakdown voltage and the specific resistance is revealed. The electric field in the body is modulated by the back gate voltage, which causes the change of the charge distribution in the body and forms a double conduction mode, which greatly improves the relationship between the breakdown voltage and the specific resistance. The trap charge conductance modulation model is proposed, and the mechanism of the back gate NBTI and the thermal carrier degradation is revealed. The field induced charge generated by the back gate NBTI and the hot carrier effect causes the change in the charge distribution in the body, which leads to the degradation of the device characteristics. The main innovations are as follows: 1. put back pressure field modulation model of gate charge modulation based on the theory, put forward the back gate field voltage modulation model, reveals the thin layer SOI high voltage field P channel LDMOS back gate voltage on the breakdown voltage and on resistance mechanism, gives the back gate voltage and breakdown voltage, guide surface the relationship between the resistance. The electric field in the body is modulated by the back gate voltage, which leads to a linear relationship between the surface breakdown voltage and the back grid voltage: BVs=0.98 x VBG 198.4. At the same time in the modulation field caused by changes in the charge distribution, the formation of double conduction mode, which makes the device specific on resistance of Ron SP depends on the conductive layer and the conductive layer drift accumulation in parallel results: Ron, sp=1/ (1.45 x 10-13 TS ND 7.07 * 10-4 VBG), has greatly improved the relationship between breakdown voltage and on resistance the. 2., put forward the criterion of back gate penetration and design criterion of device voltage, and put forward the criterion of back gate penetration. It reveals the mechanism of device's back gate perforating, and it can be applied to all SOI P channel LDMOS devices. The SOI high field P channel LDMOS device voltage design criterion, namely the power supply voltage VHV|BVs (VBG=VHV) |, |BVb| and |BVp|, considering the drain voltage and back gate voltage. The experimental results show that the breakdown voltage of the device reaches -366 V, and the specific resistance is only 6.6 Omega? Mm2. Based on the research results, we first created the thin and conductive silicon series SOI high and low voltage compatible technology of international integrated field P LDMOS, which has been applied in national defense equipment and achieved good social and economic benefits. 3., a thin layer SOI high voltage field P channel LDMOS trap charge conductance modulation model is proposed. The trap charge conductance modulation model is proposed, revealing the mechanism of the linear SOI current degradation of thin SOI high voltage field, P channel LDMOS back gate NBTI and hot carrier. The field induced charge of the back gate NBTI and the hot carrier effect causes the change of the drift area and channel charge, which leads to the degradation of the linear current. In the buried oxygen layer, the total gate positive NBTI generates the total positive field trapped charge, which reduces the accumulation layer charge density, the electric field peak and the energy band at the breakdown point, resulting in the decrease of the linear current, the increase of breakdown voltage and quiescent current. Two opposite the hot carrier effect mechanism determines the linear current degradation: hot hole injection channel in trap charge is generated, leading to increases the threshold current decreases linearly; the drift region gate field plate at the end of the hot electron injection produced negative trap charge, resulting in increased line current.
【学位授予单位】：电子科技大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN386

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